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MIT creates method to force AI to comply with safety rules
MIT researchers published HardFlow, a method enforcing hard safety constraints on flow-matching generative models' final outputs without retraining.
MIT researchers led by Zeyang Li and Navid Azizan developed HardFlow, a trajectory-optimization method that enforces strict, non-negotiable constraints on flow-matching generative models by checking rule satisfaction only at the final generation step. Published in IEEE TPAMI, it outperformed six rival projection and guidance methods on four simulated benchmarks including D3IL robotic manipulation, Maze2D, physical process control, and image editing. All results are simulation-only, with no independent reproduction yet reported.
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Retrospectively Reverse-Engineering Apple's Neural Engine
A developer reverse-engineers Apple's M1 Neural Engine architecture, mapping compute cores, MAC datapaths, and schedulers to explain the NPU's decline as transformers displaced CNN workloads.
A developer who previously maintained a reverse-engineered Linux driver for Apple's Neural Engine (ANE) published a retrospective deep dive mapping the M1 ANE's full internal architecture: compute, datapath, scheduler, memory, and execution model. The M1 ANE has 16 compute cores with 128 FP16 (or 256 INT8) MAC lanes each, totaling 2048 parallel MAC lanes, using 32-bit Q16.16 fixed-point accumulation with FP16 readout and an accumulator that saturates at 2^15. The author argues the ANE's dataflow was architected around the predictable reuse patterns of 2017-era CNN workloads (dating to the A11 Bionic), which autoregressive transformer decode broke, limiting its usefulness for general ML. With Apple's M5 folding ANE cores into GPU cores to tout LLM performance, the post frames this as the beginning of the end for the standalone NPU.
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Deep Learning-Based Detection of Electrical Faults and Power Quality Disturbances in Aerospace Power Systems
Compact ResNet detects electrical faults in 400 Hz aircraft power systems with 95.87 percent accuracy after deployment on Xilinx Zynq MPSoC.
The study targets multiclass fault and power quality disturbance detection in 400 Hz aerospace networks using a high-fidelity simulation model inspired by the Boeing 787 electrical architecture, covering 21 normal, disturbance, switching, open-circuit, and short-circuit conditions. Two 73,500-sample datasets are built from 1D waveforms and STFT time-frequency representations, augmented with domain randomization and class-specific GANs, and the time-series dataset is released via IEEE DataPort. A compact ResNet with 175,685 parameters achieved 96.94 percent software test accuracy, and 95.87 percent after 8-bit quantization on a Xilinx Zynq UltraScale Plus ZCU102 with 6.90 ms mean accelerator latency per record.
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