Search: “representations”

9 stories in the last 3d

Critical SSRF flaw in AWS SSM Agent (CVE-2026-89049) lets authenticated users bypass link-local denylists and reach EC2 Instance Metadata Service for IAM credentials.

CVE-2026-89049 (Critical, CVSS v3.1 AV:N/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:H) affects Amazon SSM Agent versions earlier than 3.3.4851.0, with the fix shipping in 3.3.4851.0. The remote-host port-forwarding feature's denylist for link-local addresses can be bypassed because equivalent address representations are not validated, enabling SSRF to restricted endpoints such as the EC2 Instance Metadata Service at 169.254.169.254. An attacker with authenticated AWS access and ssm:StartSession permission could retrieve instance profile IAM credentials and pivot to S3, Secrets Manager, Lambda, or other cloud resources depending on role permissions.

Cyber Security NewsSep 14, 15:14 UTC · 2d agoVulnerability CVE-2026-89049

You don’t have to join the hack-back program to inherit its risk

A new US presidential memorandum creates a vetted private hack-back program, leaving participating vendors and their customers with untested legal liability and collateral risks.

The August 12 National Security Presidential Memorandum directs the National Coordination Center, run jointly by DOJ and DHS, to approve covert surveillance and disruptive Cyber Effects Operations by vetted private companies, with a forfeitable bond of at least $1 million required as a contract condition. The analysis argues the criminal shield rests on an untested reading of the CFAA exemption at 18 U.S.C. 1030(f), with no civil safe harbor, no state-law preemption and no foreign-law protection. Non-participating organizations can still inherit risk through shared infrastructure collateral damage, lack of customer disclosure, Lloyd's bulletin Y5381 state-backed attack exclusions, and threat-intelligence pipelines feeding offensive proposals.

CSO OnlineSep 16, 09:00 UTC · 1d agoPolicy & legal

SEMA-GUARD: Semantic and Graph-Based Vulnerability Detection in Assembly Code

SEMA-GUARD uses semantic analysis and graph neural networks to detect vulnerabilities in assembly code, achieving 85.1% accuracy on a Juliet-derived benchmark.

SEMA-GUARD is a framework that detects vulnerabilities in compiled programs when source code is unavailable, targeting malware, firmware, and embedded systems analysis. It enriches control flow graphs with low-level execution semantics including stack manipulations, memory accesses, and data flow. Evaluated on a Juliet Test Suite set compiled to assembly and split into function-level chunks, it achieves 85.1% accuracy and an F1 score of 0.801, outperforming purely statistical or structural approaches.

arXiv cs.CRSep 15, 14:35 UTC · 1d agoResearch1

CASHEWS: Source Preprocessor for LLM-based Malicious Package Detection

CASHEWS preprocessor boosts LLM-based malicious npm package detection, raising coverage to 98.8-100% and cutting false negatives by up to 18.6 points.

Researchers present CASHEWS, a JavaScript preprocessor for LLM-based malicious package detection that deobfuscates code iteratively, extracts bundled modules and dynamically executed code, identifies malicious sinks, and computes backward slices to produce compact detector input. Threat actors evade LLM detectors by exploiting limited context windows with high token-density obfuscation and by bundling malicious code with benign packages, as seen in supply-chain attacks such as Shai-Hulud. Across 512 large package files, two scanner types, and three LLMs, CASHEWS raised analysis coverage from 69.1-85.7% to 98.8-100% and reduced false-negative rates by up to 18.6 percentage points. Median preprocessing time is 30 seconds while net analysis cost drops 34.6%.

arXiv cs.CRSep 16, 16:00 UTC · 20h agoResearch

Detecting Logic Vulnerabilities Across the Contract and Device Layers of Blockchain-Enabled IoT With Multi-Agent Heterogeneous Graph Attention

MA-HGAT framework detects logic vulnerabilities across smart contract and IoT device firmware layers using multi-agent heterogeneous graph attention.

Researchers extend MA-HGAT into a cross-layer multi-agent heterogeneous graph attention framework that models smart contracts, firmware artifacts, device fleets, and transaction streams for blockchain-enabled IoT security. A four-role, nine-relation schema supports graph-, link-, and node-level detection tasks, while a gateway-cloud partition enables lightweight edge inference on resource-constrained devices.

arXiv cs.CRSep 16, 09:08 UTC · 1d agoResearch

TasmScan: Continuation-Aware Taint Analysis for TVM Bytecode with Savelist Abstraction

TasmScan introduces source-free taint analysis for TON smart-contract bytecode, detecting 95.3% of defects with 96.8% precision and 17x speedup.

TasmScan is the first bytecode-level static analysis framework for the TON Virtual Machine, enabling cross-continuation data flow reasoning without source code by modeling savelist semantics through forward register analysis with formal over-approximation guarantees. It lifts bytecode into a typed intermediate representation (TASIR) and performs path-sensitive taint analysis. On a 208-contract benchmark with human-confirmed ground truth it detects 95.3% of defects across five classes at 96.8% precision, and resolves 294,546 dynamic continuation targets with 100% precision across 2,921 registry contracts. It achieves a 17x median speedup over symbolic-execution baselines.

arXiv cs.CRSep 15, 11:01 UTC · 2d agoResearch1

New DDRop Attack Breaks Intel TDX and AMD SEV-SNP With $159 DDR5 Device

DDRop uses a $159 DDR5 RDIMM interposer to silently drop memory writes and break Intel TDX and AMD SEV-SNP confidential VMs.

Researchers published DDRop, a physical attack built from about $159 in parts that uses a custom DDR5 RDIMM interposer to inject parity errors and silently discard selected cache-line writebacks. Intel TDX, Intel Scalable SGX, and AMD SEV-SNP are affected because they lack per-line cryptographic freshness, so processors can accept stale encrypted data as valid state. The team demonstrated deterministic plaintext copying between pages, malicious Secure EPT entry injection, forcing trust domains into debug mode, and forging attestation measurements. The attack requires privileged host control plus brief physical access, and researchers say no simple software patch exists.

Cyber Security NewsSep 15, 09:57 UTC · 2d agoResearch 2 sources

DDRop Attack Forces Intel TDX Confidential VMs Into Debug Mode and Exposes Memory

KU Leuven and ETH Zurich researchers released DDRop PoC hardware that forces Intel TDX confidential VMs into debug mode and exposes plaintext memory.

Researchers from KU Leuven, ETH Zurich, Google, and Durham University published proof-of-concept code, hardware designs, and firmware for DDRop, a DDR5 interposer that injects parity errors to drop selected cache-line writebacks. Because Intel TDX, Intel Scalable SGX, and AMD SEV-SNP lack per-line cryptographic freshness, processors decrypt and accept stale DRAM contents as current state. The PoC flips a victim's ATTRIBUTES.DEBUG flag to enable TDX debug mode, then copies victim memory in plaintext and can forge attestation reports. Affected environments include Intel 5th- and 6th-generation Xeon Scalable with TDX; Intel says the attack falls outside its cloud-computing threat model.

GBHackersSep 15, 09:57 UTC · 2d agoResearch

No Bit Left Behind: Using Brute-Force Lifting to Achieve Fully Static Binary Recompilation

Prototype binary lifter brute-force lifts every byte offset of x86-64 binaries to LLVM IR, enabling fully static cross-ISA recompilation without runtime support.

The paper presents a fully static, whole-program binary lifting system that treats every byte offset as a potential branch target, constructing a superset control flow graph that conservatively contains all feasible control flows. Statically unresolvable computed branches are reduced to lookups in a dispatch table pointing to translated control flow paths, eliminating runtime translation machinery on the target machine. A prototype recompiles x86-64 binaries to LLVM IR with no code/data heuristics and achieves fully static cross-compilation to AArch64 using unmodified LLVM backends.

arXiv cs.CRSep 14, 23:00 UTC · 2d agoResearch1