Search: “fpga”

Chypothermia: Clock Freezing for Static Side-channel Attacks

Chypothermia attack uses cryogenic cooling to disable clock and voltage sensors, evading detection and blocking key zeroization on OpenTitan root of trust.

Chypothermia is a static side-channel attack that exposes chips to cryogenic temperatures, disrupting on-chip mixed-signal components to disable the clock sensor, clock generation circuit, and voltage sensors without electrical tampering. Combined with Chypnosis (IEEE S&P 2026), it halts the clock while evading temperature-based anomaly detection. It was implemented on multiple FPGA/SoC platforms and applied to the OpenTitan root of trust's alert handler, evading detection and preventing key zeroization. The authors also propose an FPGA-compatible self-heating sensor as a countermeasure.

arXiv cs.CR·Sep 10, 12:12 UTC · 5d agoResearch

CHERI-D Reincarnate: efficient multicore CHERI temporal memory safety through allocation reincarnation (draft version)

CHERI-D Reincarnate adds allocation reincarnation to CHERI, quarantining generation IDs instead of memory to cut temporal memory-safety overheads on multicore systems.

The proposal extends CHERI-D temporal memory safety by quarantining exhausted generation IDs rather than memory slots, allowing freed memory immediate reuse through allocation reincarnation. It adds coherent ID caching and multicore support connecting physical coherence events to the virtually addressed ObjID buffer. The design was implemented as a hardware-software co-design across CHERI-Toooba FPGA softcore, QEMU, LLVM/Clang, and CheriBSD. Across evaluated workloads it substantially reduces memory-sweep frequency and quarantine overhead with low performance and hardware cost.

arXiv cs.CR·Sep 10, 14:19 UTC · 5d agoResearch

FreqSpaNet: Frequency and Spatial Learning of SFPF for Physical Layer Hardware Integrity Detection

FreqSpaNet learns spatio-frequency polarization fingerprints to detect unauthorized wireless hardware replacement, reaching 96.31% mean AUROC across seven replacement scenarios.

FreqSpaNet is a representation learning network for open-set hardware anomaly detection using spatio-frequency polarization fingerprints (SFPFs), which capture device-dependent responses across frequencies and directions. A frequency branch models local variations among neighboring frequencies while a geometry-aware spatial branch models directional relationships via angular information, combined through adaptive fusion and complementary pretraining. It achieves a mean AUROC of 96.31%, 9.05 points above the baseline, and is verified under seven hardware replacement scenarios.

arXiv cs.AI / cs.LG / cs.CL·Sep 15, 17:32 UTC · 18h agoAI research

FOMO in the SOC: Where AI Platforms like Claude Actually Fit

The Hacker News·Aug 3, 11:30 UTC · Aug 3, 2026Malware

CertiFlash: A Formal Verification Framework for Flash Translation Layers in Computational Solid State Drives

CertiFlash provides machine-checked formal verification of SSD flash translation layers, proving isolation, integrity, and ownership invariants to prevent tenant data leaks.

CertiFlash is an open-source formal verification framework for Flash Translation Layers (FTL) in computational SSDs, mechanized in the Rocq proof assistant. It shows that a faulty FTL can corrupt device state at five surfaces (e.g., leaking data between tenants or dropping integrity tags), demonstrated on a DaisyPlus OpenSSD. Designers prove once that every operation of a general FTL model preserves a global invariant covering mapping, isolation, integrity, ownership, and allocation; new designs need only discharge five hypotheses. Across four case studies, added effort was 27-3,231 lines against a 16,489-line framework.

arXiv cs.CR·Sep 9, 15:44 UTC · 6d agoResearch1

Securing the Infrastructure of Intelligence

NVIDIA positions AI factories combining chips, networking, power and data as the defining infrastructure of the AI economy needing full-stack security.

NVIDIA's blog argues that AI factories are the defining infrastructure of the AI era, transforming energy and data into intelligence that powers businesses and countries. It frames compute as revenue and lists the full stack of critical resources required: advanced chips, packaging, memory, networking, land and power. The piece is a corporate positioning article about securing this infrastructure, with no specific incident or product announcement detailed in the excerpt.

NVIDIA Blog·Aug 17, 12:34 UTC · 29d agoAI industry

Delivering Vera: NVIDIA’s First CPU Built for Agents Is Shipping Now

NVIDIA's Vera CPU, its first processor built for AI agents, is now shipping at scale to partners across the AI ecosystem.

NVIDIA announced that Vera, its first CPU designed specifically for agentic AI workloads, has begun shipping at scale. Vice President of Hyperscale and HPC Ian Buck is hand-delivering early Vera CPU systems to organizations across the AI ecosystem, signaling full production availability of the data-center processor.

NVIDIA Blog·Aug 27, 13:00 UTC · 19d agoAI industry

Linux Foundation takes on TRACE, a hardware-backed runtime evidence specification for AI agents

The Linux Foundation adopts TRACE, an OPAQUE-contributed spec giving AI agents hardware-attested, cryptographically verifiable runtime and compliance evidence.

The Linux Foundation accepted the TRACE (Trust, Runtime Attestation and Compliance Evidence) specification contributed by OPAQUE, developed with AMD, Intel, Microsoft, and the Technology Innovation Institute. TRACE binds runtime environment, software, policies, data classifications, and tool usage into a portable, cryptographically verifiable artifact, composing existing standards such as RATS, EAT, SLSA, SCITT, SPIFFE, and EAR. It recorded nearly 135,000 PyPI downloads within 10 weeks of its June 2026 introduction, and its technical workstream will be hosted by the Coalition for Secure AI.

Help Net Security·Aug 26, 00:00 UTC · 21d agoAI tools & infra

Why Scaling AI Compute Performance Requires a New Power Architecture

NVIDIA argues AI factories need 800 VDC power distribution as dense GPU racks outgrow traditional AC-based delivery.

NVIDIA's blog contends each generation of accelerated computing demands higher rack density and more efficient, scalable power distribution. It frames the bottleneck as how power moves from the grid to the GPU rather than raw wattage, and describes limitations of traditional AC power delivery. NVIDIA advocates a new 800 VDC power architecture for AI factories.

NVIDIA Blog·Aug 11, 15:00 UTC · Aug 11, 2026AI industry

Speculative Decoding in vLLM on AMD GPUs

vLLM benchmarks speculative decoding on AMD Instinct MI300X and MI355X GPUs across five drafting methods including EAGLE-3 and native MTP.

The vLLM project documents draft-and-verify speculative decoding support for AMD GPUs via ROCm, comparing native MTP, Gemma 4 MTP, EAGLE-3, DFlash, and DSpark drafting approaches. Output-token throughput effects varied with drafting method, proposal length, model family, draft checkpoint, workload, and acceptance behavior. The post also covers how to enable each method plus practical tuning and observability considerations.

Hacker News · AI·Sep 7, 09:26 UTC · 9d agoAI tools & infraHN 141↑ · 52 comments1

[AINews] Hot Chips: OpenAI’s Jalapeño, Cerebras CS-5, Groq 3 LPX, Apple M6

OpenAI unveiled Jalapeno custom inference chip claiming 1.5-1.9x better perf-per-watt than NVIDIA GB200/GB300, deploying in-house by year-end.

At the 37th Hot Chips conference, OpenAI published first benchmark details for its custom Jalapeno inference chip, claiming 1.5-1.9x more work per watt, 1.7-3.6x lower end-to-end latency, and 2.1-4.1x higher interactive-workload performance versus NVIDIA GB200/GB300, with the 700W-rated part staying at or below 550W in tests. Deployment into OpenAI's own infrastructure begins by year-end, with Gen 2 deep in development and Gen 3 underway. OpenAI also said GPT-Astra and Codex helped write low-level kernels, reportedly 1.5-1.8x faster than human-expert code for selected attention and MoE blocks. Cerebras CS-5, Groq 3 LPX and Apple M6 were also featured at the conference.

Latent Space·Aug 27, 01:31 UTC · 20d agoAI industry

Linux Foundation Introduces TRACE Standard for AI Runtime Evidence

The Linux Foundation introduced TRACE, an open standard providing hardware-attested runtime and compliance evidence for AI agents.

The Linux Foundation announced TRACE, an open standard designed to generate hardware-attested runtime evidence for AI agents. The standard aims to give auditors and regulators verifiable proof of what AI agents actually executed. It targets compliance and assurance needs for organizations deploying autonomous AI systems.

Infosecurity Magazine·Aug 26, 09:10 UTC · 21d agoAI tools & infra1

[hardware] Fullhan FH8626V100 - Multiple Vulnerabilities

Multiple vulnerabilities in the Fullhan FH8626V100 hardware chip have been disclosed alongside public proof-of-concept exploits.

Exploit-DB lists an entry covering multiple vulnerabilities in the Fullhan FH8626V100, a hardware component. The listing provides no CVE ids, vulnerability classes, or evidence of in-the-wild exploitation. Impact is likely limited to devices embedding the affected chip.

Exploit-DB·Sep 2, 00:00 UTC · 14d agoExploit / PoC

The OCUDU dApp Platform: An Open Runtime and E3 Interface for Real-Time AI-RAN

OCUDU open runtime lets third-party signed AI-RAN dApps run inside production 5G distributed units under three timing contracts, released as BSD-3 preview.

The OCUDU dApp platform provides an open runtime and E3 interface for executing signed AI-RAN applications inside a production 3GPP NR distributed unit, where prior dApp frameworks could only observe export streams. Modules run under three typed timing contracts: GPU receive-chain residency (Class A), the scheduler's 100 microsecond deadline (Class B), or non-blocking observer (Class C). On a GB10 gNB, dApps including an out-of-tree neural equalizer ran on a live cell without fallback. Platform, SDK, and a zero-hardware quickstart are public under BSD-3-Clause-Clear as a preview of the OCUDU AI-RAN Working Group 2.

arXiv cs.AI / cs.LG / cs.CL·Sep 7, 18:03 UTC · 8d agoAI tools & infra1

SCHERI: Provably Secure Speculation Under the Constant-Time Policy for CHERI (Extended Version)

Researchers formally prove existing CHERI speculation proposals leak secrets and present SCHERI, a processor design with end-to-end Spectre-resistant constant-time guarantees.

The paper builds a formal framework reasoning jointly about capability safety, speculative execution, and information-flow security on CHERI architectures. It demonstrates that existing secure-speculation proposals fail to preserve constant-time confidentiality guarantees and can transiently leak isolated secrets. The authors present SCHERI, a new processor design formally proven to provide end-to-end secure speculation for the constant-time policy, resilient to Spectre attacks.

arXiv cs.CR·Sep 15, 16:33 UTC · 19h agoResearch

Event-Native Symbolic-Temporal Spike Encoding Framework for Heterogeneous Cyber Streams

An event-native spike encoding framework lets recurrent spiking neural networks run intrusion detection directly on heterogeneous packet and CAN bus streams.

The paper maps heterogeneous cyber events—categorical identifiers, local frequency context, and inter-event timing—directly into sparse spike-compatible inputs for spiking neural networks. This avoids flow aggregation and fixed windows that add buffering latency and obscure temporal structure in traditional IDS pipelines. Compact recurrent SNNs under edge-oriented neuromorphic hardware constraints achieve a hybrid anomaly metric of 0.987 on packet-level Network IDS and 0.980 on message-level CAN IDS.

arXiv cs.CR·Sep 14, 15:55 UTC · 1d agoResearch

How XPUs Meet a World-Class AI Factory

NVIDIA argues AI factories with custom XPUs and NVLink Fusion connectivity must optimize tokens-per-second, tokens-per-watt, cost and uptime.

NVIDIA published a blog explaining that AI factories running continuously are economically defined by delivered output: tokens per second, tokens per watt, cost per token, utilization and uptime. It argues hyperscalers and AI-native companies building custom XPUs need infrastructure designed as a complete factory rather than collections of individual accelerators. The piece promotes NVIDIA's NVLink Fusion and full-stack XPU connectivity as the foundation for such world-class AI factory builds.

NVIDIA Blog·Aug 24, 15:00 UTC · 22d agoAI industry

Deep Learning-Based Detection of Electrical Faults and Power Quality Disturbances in Aerospace Power Systems

Compact ResNet detects electrical faults in 400 Hz aircraft power systems with 95.87 percent accuracy after deployment on Xilinx Zynq MPSoC.

The study targets multiclass fault and power quality disturbance detection in 400 Hz aerospace networks using a high-fidelity simulation model inspired by the Boeing 787 electrical architecture, covering 21 normal, disturbance, switching, open-circuit, and short-circuit conditions. Two 73,500-sample datasets are built from 1D waveforms and STFT time-frequency representations, augmented with domain randomization and class-specific GANs, and the time-series dataset is released via IEEE DataPort. A compact ResNet with 175,685 parameters achieved 96.94 percent software test accuracy, and 95.87 percent after 8-bit quantization on a Xilinx Zynq UltraScale Plus ZCU102 with 6.90 ms mean accelerator latency per record.

arXiv cs.AI / cs.LG / cs.CL·Sep 9, 17:19 UTC · 6d agoAI research

How CHERIoT Provides Strong and Usable Isolation Without an MMU

ACM Queue paper explains how CHERIoT uses CHERI hardware capabilities to give microcontroller-class IoT devices memory and privilege isolation without an MMU.

The ACM Queue article (DOI 10.1145/3831361) describes CHERIoT, a RISC-V-derived platform that scales CHERI capability-based hardware down to small embedded and IoT microcontrollers. It provides strong, fine-grained isolation and memory safety without a memory management unit, aiming to make compartmentalization practical for low-cost devices. The piece emphasizes usability of the isolation model alongside its security guarantees.

Lobsters · security·Sep 10, 14:59 UTC · 5d agoResearch

Hardware Fingerprinting FTQC via Quantum Decoder Timing

Quantum decoder timing on IBM Heron processors forms a side channel enabling device fingerprinting with 89% accuracy and workload inference.

The work demonstrates that wall-clock syndrome-decoding times on fault-tolerant quantum computers constitute a novel hardware side channel. Using per-shot decoder timings from three IBM Heron processors collected over 68 days, a passive observer can reconstruct detector-firing distributions, estimate logical error rate, infer code distance, and fingerprint the specific device with up to 89% accuracy versus 33% for random guessing. Noisy simulation based on Google's 105-qubit Willow processor distinguishes nine surface-code patches at 81% accuracy, showing the channel persists across vendors and code families.

arXiv cs.CR·Sep 10, 19:24 UTC · 5d agoResearch

Jalapeño’s first results show industry-leading speed and efficiency in AI inference

OpenAI's Jalapeño custom inference chip shows faster, more power-efficient inference with higher throughput and lower latency.

OpenAI announced first results for Jalapeño, its custom AI inference chip. The company claims industry-leading speed and efficiency, delivering higher throughput and lower latency for modern models compared with existing options. The chip targets more power-efficient serving of large models at scale.

OpenAI News·Aug 25, 07:00 UTC · 22d agoAI industry

FreeFlow: A Bias-free Hierarchical Transformer for Optical Flow Estimation

FreeFlow is a bias-free hierarchical transformer achieving state-of-the-art optical flow results on Sintel, KITTI-2015, and Spring benchmarks.

FreeFlow replaces task-specific inductive biases like correlation volumes and iterative warping with a single feed-forward encoder-decoder combining window, shifted-window, and reduced-resolution global attention. It reaches 0.68/1.48 EPE on Sintel Clean/Final, 3.23 Fl-all on KITTI-2015, and 3.192 1px on Spring. The architecture scales consistently from small to large variants and remains memory efficient at 1080p inference.

Hugging Face daily papers·Sep 9, 20:00 UTC · 6d agoAI research

FST Pay: Deterministic Safety-Gated Architecture for Youth Digital Payments

FST Pay proposes a deterministic safety-gated architecture for teen digital payments, pairing invariant authorization checks with decoupled post-settlement AI explanations.

Researchers propose FST Pay, a formal architecture for adolescent digital payments on rails like UPI that applies six deterministic invariant checks (spending limits, guardian co-sign policies, amount thresholds, merchant category codes, temporal intervals, hardware integrity) to classify transactions as ALLOW, REVIEW, or BLOCK. High-risk transactions trigger an asynchronous guardian co-sign workflow. Generative AI is restricted to post-settlement natural-language insights and holds no mutation privileges over the ledger, avoiding non-determinism on the real-time authorization path.

arXiv cs.CR·Sep 10, 08:03 UTC · 6d agoResearch

The Regulators Already Assume You Have an AI Inventory. Do You?

Checkmarx argues regulators now expect organizations to maintain an AI inventory as AI-generated code and outputs enter security workflows.

Checkmarx contends that implicit trust in AI-generated code, AI summaries, and scanner output has become a governance liability that regulators no longer accept. The piece argues security teams must formalize AI inventories and treat AI outputs as untrusted inputs. It frames AI governance as an emerging compliance expectation rather than an internal maturity project.

Checkmarx·Aug 26, 09:15 UTC · 21d agoAI policy1

Understanding the Security Boundary of Obfuscation-based On-Device LLM Protection

Researchers formalize obfuscation primitives for TEE-protected on-device LLMs and show a Collapse attack breaks ArrowCloak, TSQP, and LoRO, then extend the boundary.

The paper formalizes obfuscation primitives for TEE-Shielded LLM Partition (TSLP) schemes that offload computationally intensive layers from a Trusted Execution Environment to external GPUs. A novel primitive-guided attack, Collapse, demonstrates a shared vulnerability in prominent published methods including ArrowCloak (Security'25), TSQP (S&P'25), and LoRO (NeurIPS'25). The authors then introduce two new obfuscation primitives and integrate them with existing constructs to formulate an extended security boundary (O_ext).

arXiv cs.CR·Sep 9, 12:51 UTC · 6d agoAI safety & security

Salesforce and Nvidia’s new reasoning model is everything the AI labs should fear

Salesforce and Nvidia launch Koa, Salesforce's first reasoning model, built on Nvidia's open-weight Nemotron and post-trained on synthetic sales and support data.

Salesforce announced Koa at Dreamforce, its first reasoning model, built on Nvidia's open-weight Nemotron and post-trained with synthetic data mimicking sales and customer-support scenarios rather than real customer data. Koa will be offered through the Agentforce platform's AI gateway as a cheaper, token-efficient alternative to closed frontier models like Claude and ChatGPT for enterprise tasks. Salesforce simultaneously announced a ClaudeForce partnership with Anthropic keeping customer data inside Salesforce's infrastructure.

TechCrunch · AI·Sep 15, 12:00 UTC · 1d agoModel release1

Retrospectively Reverse-Engineering Apple's Neural Engine

A developer reverse-engineers Apple's M1 Neural Engine architecture, mapping compute cores, MAC datapaths, and schedulers to explain the NPU's decline as transformers displaced CNN workloads.

A developer who previously maintained a reverse-engineered Linux driver for Apple's Neural Engine (ANE) published a retrospective deep dive mapping the M1 ANE's full internal architecture: compute, datapath, scheduler, memory, and execution model. The M1 ANE has 16 compute cores with 128 FP16 (or 256 INT8) MAC lanes each, totaling 2048 parallel MAC lanes, using 32-bit Q16.16 fixed-point accumulation with FP16 readout and an accumulator that saturates at 2^15. The author argues the ANE's dataflow was architected around the predictable reuse patterns of 2017-era CNN workloads (dating to the A11 Bionic), which autoregressive transformer decode broke, limiting its usefulness for general ML. With Apple's M5 folding ANE cores into GPU cores to tout LLM performance, the post frames this as the beginning of the end for the standalone NPU.

Hacker News · AI·Sep 12, 07:54 UTC · 4d agoAI researchHN 54↑ · 7 comments2

MathKernel: An evidence-aware multi-engine mathematics kernel and MCP server

MathKernel is an open-source, evidence-aware multi-engine mathematics kernel that exposes verification workflows to AI agents via an MCP server.

MathKernel, published on GitHub, is a mathematics kernel that combines multiple computation engines with evidence-aware outputs. It ships as an MCP server, enabling AI agents and coding assistants to perform and verify calculations. The project drew moderate attention on Hacker News.

Hacker News · security·Sep 7, 00:21 UTC · 9d agoAI tools & infraHN 36↑ · 5 comments

New hardware device can RAM into encrypted memory, expose your data

Researchers built a $200 DDR5 interposer that silently drops memory writes to break TDX, SGX, and SEV-SNP confidential VM integrity, requiring physical access.

Researchers from KU Leuven, ETH Zurich, Durham University, and Google demonstrated DDRop, a hardware interposer costing under $200 that corrupts DDR5 bus commands to silently drop writes to encrypted memory, enabling replay attacks on confidential VMs. Because scalable memory encryption lacks freshness checks, protected VMs keep computing on stale attacker-selected data; on an Intel TDX server the attack forces debug mode for plaintext memory reads or forges attestation reports, succeeding in under two minutes without crashing. Intel and AMD both called the attack out of scope for their cloud threat models, with no mitigation planned, and proposed cache line versioning appears still vulnerable. The full interposer design is being released as open-source hardware.

The Register · Security·Sep 14, 18:31 UTC · 1d agoResearch

OPEN-1B: A Fully Auditable Training Run

Open-1B releases a 1B-parameter model with bitwise-reproducible training, letting independent auditors verify every step of the run on commodity hardware.

The paper introduces a 'fully auditable' tier of model transparency: every training operation is reproducible with bitwise certainty on heterogeneous commodity hardware by imposing definite ordering on GPU kernel reductions, data batch ordering, and collective communication. Because replaying a full run on one machine is infeasible, a collective verification scheme lets many independent auditors certify individual steps covering the whole run. The authors release Open-1B with its full pretraining dataset, every intermediate checkpoint, the training codebase, and an audit harness. This rules out undisclosed data, injected biases, or backdoors that proof-of-learning or proof-of-training-data techniques cannot exclude.

arXiv cs.AI / cs.LG / cs.CL·Sep 15, 16:23 UTC · 19h agoAI research