Reversing the Clock: Layout-Aware Recovery of Design Intent from Clock Distribution Networks
Layout-aware pipeline recovers clock distribution networks from a fabricated 450 nm IC via SEM imagery and netlist recovery, exposing topology, gating, and designer intent.
The paper presents a four-phase, layout-aware methodology that integrates a recovered gate-level netlist with layout data extracted from scanning electron microscope imagery to reconstruct an IC's clock distribution network. The pipeline recovers clock-tree topology, buffering, gating and switching, interconnect delay, and crosstalk-mitigation measures. Demonstrated on a commercial 450 nm IC, it recovered a global H-tree backbone with X-tree-like local branching, an independent clock tree, and global clock gating, while quantifying latency, skew, and routing lengths. The clock tree recovery algorithm is released as open source.
- First published work recovering clock networks from fabricated ICs to infer design intent
- Recovers topology, buffering, gating, interconnect delay, and crosstalk mitigation measures
- Validated on commercial 450 nm IC; found H-tree backbone and global clock gating
- Clock tree recovery algorithm released as open source
From the original article
1 min read at arxiv.orgHardware reverse engineering supports competitive analysis and hardware assurance by recovering information about an integrated circuit (IC) from its physical implementation. While existing techniques primarily recover the gate-level netlist, which represents logical functionality, they often overlook physical design decisions such as placement, routing, delay insertion, and interconnect optimization.
By Sascha Tommasone · arxiv.org
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