VU#431093: TCG TPM 2.0 reference code found vulnerable to information leakage and timing side-channel attacks
CERT/CC discloses two TPM 2.0 reference code flaws allowing RSA key decryption and forged TPM attestations via crafted commands.
CERT/CC published VU#431093 covering two vulnerabilities in the TCG TPM 2.0 reference implementation: CVE-2026-6726 (information leakage via falsified TPM keys) and CVE-2026-6727 (timing side-channel in RSA OAEP decryption). An attacker with privileged access to a TPM command interface could send crafted TPM commands to decrypt ciphertexts for affected TPM-managed RSA keys, including the RSA Endorsement Key, or obtain credentials enabling forged TPM 2.0 attestations. Remediation is tracked in TCGVRT010 and TCGVRT0011.
- CVE-2026-6726 leaks information via falsified TPM keys
- CVE-2026-6727 is a timing side-channel in RSA OAEP decryption
- Enables decryption of TPM-managed RSA keys and forged attestations
- Requires privileged access to the TPM command interface
Vulnerabilities mentionedAll →
| CVE | Vulnerability | CVSS | EPSS | Flags | Affected | Exposure | Published |
|---|---|---|---|---|---|---|---|
| CVE-2026-6726 | Info Leak in TCG TPM 2.0 Reference Code Enables Attestation Key Forgery An information-leakage flaw in the Trusted Computing Group's TPM 2.0 reference code (tracked by TCG as VRT0010 and by CERT/CC as VU#431093) allows a local attacker with elevated privileges to obtain a credential from a TPM-aware certificate authority for a falsified TPM key. It is triggered locally on systems whose TPM runs code derived from the TCG reference implementation when the attacker manipulates key-attestation flows for keys such as an Attestation Key, DevID Key, or TLS authentication key. With the fraudulently issued credential, the attacker can falsify other TPM 2.0 attestations with that key, undermining device-identity and attestation guarantees. Any deployment of the TCG TPM 2.0 reference code - including commercial TPM chips, firmware TPMs, and TPM-aware CA/attestation infrastructure - is potentially affected; the available data does not specify version ranges. No exploitation has been observed: there is no public proof-of-concept, the issue is not in CISA's KEV, and EPSS estimates only a ~0.2% chance of exploitation in the next 30 days. Do: Track TCG VRT0010/VU#431093 and apply TPM/BIOS firmware updates from your PC or TPM vendor as they become available; Microsoft's August 2026 Patch Tuesday batch (398 CVEs) is among related releases, so verify whether your platform's TPM fix shipped there. Prioritize environments that use TPM key attestation with a CA (EK/AK, DevID, or TLS client certificates) and restrict local administrative privileges until patched. Audit attestation credentials issued by TPM-aware CAs for keys that may have been falsified. | 7.9 | <1% |
| masshundreds of millions of devices (TPM 2.0 is standard on modern PCs, and many TPM chips and firmware TPMs derive from the TCG reference code) | ||
| CVE-2026-6727 | Timing Side-Channel in TCG TPM 2.0 Reference Code RSA-OAEP Decryption CVE-2026-6727 is a timing side-channel vulnerability (CWE-208, tracked as TCGVRT0011) in the RSA OAEP decryption implementation of TPM 2.0 code derived from the Trusted Computing Group reference implementation. A privileged local attacker with access to the TPM command interface can measure timing differences across decryption operations to recover information sufficient to decrypt ciphertexts encrypted to TPM-managed RSA keys, including the RSA Endorsement Key (EK), import blobs, credential blobs, and session salts. Under certain conditions, the leaked information may also enable forgery of TPM 2.0 attestations, undermining trust in remote-attestation results. Any platform whose TPM 2.0 firmware is built from the affected TCG reference code is potentially affected, which spans TPM silicon from multiple vendors shipped across modern PCs, laptops, and servers; per-vendor exposure depends on whether the vulnerable code path was adopted. No public proof-of-concept or known exploitation exists (EPSS 0.2% over 30 days, not in CISA KEV). Do: Inventory devices by TPM vendor/model and monitor for TPM firmware or driver fixes tied to TCGVRT0011 and VU#431093; apply updates from the device or silicon vendor as they are released, potentially surfacing through OS patch channels such as Microsoft's August 2026 Patch Tuesday. Until patched, restrict local privileged access to the TPM command interface to trusted code and weigh the risk of relying on TPM attestation for high-assurance operations. With no known exploitation and a high-complexity, local attack requirement, treat this as standard patch-cycle priority rather than an emergency. | 5.9 | <1% |
| mass≈100M+ devices (TPM 2.0 chips ship as standard in modern PCs, laptops, and servers; confirmed per-vendor counts unknown) |
Overview Two vulnerabilities have been identified in the Trusted Platform Module (TPM) 2.0 reference implementation: CVE-2026-6726 – Information leakage via falsified TPM keys. CVE-2026-6727 – A timing side-channel vulnerability in RSA OAEP decryption. An attacker with privileged access to a TPM command interface may be able to exploit these vulnerabilities by sending specially crafted TPM commands. Successful exploitation could allow the attacker to decrypt ciphertexts encrypted to affected TPM-managed RSA keys, including the RSA Endorsement Key (EK), or obtain credentials for falsified TPM keys, enabling forged TPM 2.0 attestations. TCGVRT010 and TCGVRT0011: Description Trusted Platform…
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