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New TCG guidance gives buyers a way to test PQC-ready TPM claims

Trusted Computing Group published PTP 1.07-based requirements defining PQC-ready and PQC-upgradable TPM designations to guide buyers assessing quantum-safe hardware.

The Trusted Computing Group published requirements establishing PTP 1.07, based on TPM 2.0 Library Specification Version 1.85, as the baseline for a 'TCG PQC-ready TPM', and defined a second designation, 'TCG PQC-upgradable TPM', for chips that can be upgraded to that support. The guidance lets buyers request vendor evidence that TPMs meet end-to-end post-quantum requirements for identities, attestation, and hardware-anchored trust rather than single-algorithm compliance. TCG also announced plans to extend its certification programs to certify TPMs meeting PTP 1.07, noting that 90% of businesses still lack a formal PQC roadmap.

Help Net Security · 22d agoTools

VU#431093: TCG TPM 2.0 reference code found vulnerable to information leakage and timing side-channel attacks

CERT/CC discloses two TPM 2.0 reference code flaws allowing RSA key decryption and forged TPM attestations via crafted commands.

CERT/CC published VU#431093 covering two vulnerabilities in the TCG TPM 2.0 reference implementation: CVE-2026-6726 (information leakage via falsified TPM keys) and CVE-2026-6727 (timing side-channel in RSA OAEP decryption). An attacker with privileged access to a TPM command interface could send crafted TPM commands to decrypt ciphertexts for affected TPM-managed RSA keys, including the RSA Endorsement Key, or obtain credentials enabling forged TPM 2.0 attestations. Remediation is tracked in TCGVRT010 and TCGVRT0011.

New Guidance Helps Businesses Verify Quantum-Safe Hardware Claims

TCG issued guidance to help businesses verify that trusted platform modules genuinely meet quantum-safe requirements.

The Trusted Computing Group (TCG) published new guidance aimed at proving that trusted platform modules (TPMs) genuinely satisfy essential quantum-safe requirements. The document gives businesses a way to validate vendor claims about post-quantum readiness in hardware security rather than trusting marketing assertions. This is a guidance publication, not an incident or vulnerability disclosure.

Infosecurity Magazine · 22d agoAdvisory

Testing race conditions with memory access tracing and stack-based delay injection

Google Project Zero released MAccConc, Linux kernel tooling that traces memory accesses to explore and test race condition interleavings.

A Google Project Zero researcher published MAccConc (Memory Access Concurrency), tooling for exploring possible interleavings of multithreaded test cases in the Linux kernel, available on GitHub. The tools use KCOV with ASAN outline-mode instrumentation to record per-access memory traces, enabling automatic testing of all A-B-A interleavings plus terminal and GUI explorers for manual analysis. The work targets confirming race condition candidates, building reliable regression tests, and enabling concurrency fuzzing, drawing on ideas from SKI and Ned Williamson's sockfuzzer.

Google Project Zero · 8d agoResearch1