PhotoFinish enables portable timerless probing of microarchitectural latencies
Original title: PhotoFinish: Portable Timerless Probing of Microarchitectural Latencies
Converts latency differences into architectural values via parallel threads and shared memory.
PhotoFinish races an operation under test against a fixed reference in two parallel threads that write unique values to the same shared location. This produces a latency-dependent architectural value without timers or clocks. The method generalizes across 38 CPUs spanning four ISAs, works in WebAssembly inside browsers, and applies to caches, TLBs and execution engines.
- Reliable cache state classification across 38 CPUs
- Comparable fidelity in browsers via WebAssembly
- Applies to TLB and execution-engine latencies
- Sufficient precision to identify LLC slice
From the original article
1 min read at arxiv.orgTiming measurements are a fundamental building block of microarchitectural attacks, enabling software to convert otherwise invisible latency differences into architectural observations. Thus, restricting high-resolution timers is a common defense, especially in constrained environments such as web browsers. Timerless probing primitives provide an alternative approach.
By Tristan Hornetz · arxiv.org
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