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Locus: A Framework for Exploring and Optimizing Point Addition Hardware for Zero-Knowledge Proofs
Locus framework automates ASIC and FPGA point-addition designs for elliptic curves, achieving 2.71x speedups and 3.11x area reductions for ZKPs.
Locus is a framework that automatically generates ASIC and FPGA implementations of elliptic curve point addition (PADD) for supported equation forms, enabling exploration of over 1,000 design points. On a 12nm technology node, its designs achieve a 2.71x geomean speedup and 3.11x geomean area reduction versus prior ASICs, plus 34.67x geomean speedup over CPU. Integrated into a prior ZKP accelerator at iso-area, it yields a 3.15x geomean speedup on end-to-end proof generation. The framework is open source on GitHub.
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