Locus: A Framework for Exploring and Optimizing Point Addition Hardware for Zero-Knowledge Proofs
Locus framework automates ASIC and FPGA point-addition designs for elliptic curves, achieving 2.71x speedups and 3.11x area reductions for ZKPs.
Locus is a framework that automatically generates ASIC and FPGA implementations of elliptic curve point addition (PADD) for supported equation forms, enabling exploration of over 1,000 design points. On a 12nm technology node, its designs achieve a 2.71x geomean speedup and 3.11x geomean area reduction versus prior ASICs, plus 34.67x geomean speedup over CPU. Integrated into a prior ZKP accelerator at iso-area, it yields a 3.15x geomean speedup on end-to-end proof generation. The framework is open source on GitHub.
- Automatically generates ASIC and FPGA point-addition implementations for any supported elliptic curve equation form.
- 2.71x geomean speedup and 3.11x area reduction versus prior ASICs on 12nm node.
- 3.15x geomean speedup on end-to-end proof generation integrated into a prior ZKP accelerator.
- First comprehensive hardware-focused study spanning over 1,000 point-addition design points.
Full article177 words · extracted from arxiv.org · click to collapse
Zero-Knowledge Proofs (ZKPs) are critical for privacy-preserving and verifiable computation, but their cryptographic primitives impose high computational overheads. One such primitive is point addition (PADD) on elliptic curves. Several prior works have implemented PADDs in hardware, but only for a few specific elliptic curves and design points, leaving a large design space unexplored, and lacking systematic guidance on hardware design trade-offs. To address this gap, we present Locus, a framework dedicated to optimizing and exploring point addition hardware. Given the parameters of any elliptic curve in a supported equation form, Locus automatically generates ASIC and FPGA implementations of PADD, enabling systematic exploration of the PADD design space. Using Locus, we conduct the first comprehensive hardware-focused study of PADD designs, exploring trade-offs over 1,000 design points. On a 12nm technology node, our framework produces PADD designs that yield a $2.71\times$ geomean speedup and $3.11\times$ geomean area reduction compared to prior ASICs, $34.67\times$ geomean speedup over CPU, and $3.15\times$ geomean speedup on end-to-end proof generation when integrated into a prior ZKP accelerator at iso-area. Locus is available at https://github.com/cryptolets/cryptolets/tree/locus.
Text extracted automatically; images, tables and formatting may be missing. Original: https://arxiv.org/abs/2609.18846