Locus: A Framework for Exploring and Optimizing Point Addition Hardware for Zero-Knowledge Proofs
Locus framework automates ASIC and FPGA point-addition designs for elliptic curves, achieving 2.71x speedups and 3.11x area reductions for ZKPs.
Locus is a framework that automatically generates ASIC and FPGA implementations of elliptic curve point addition (PADD) for supported equation forms, enabling exploration of over 1,000 design points. On a 12nm technology node, its designs achieve a 2.71x geomean speedup and 3.11x geomean area reduction versus prior ASICs, plus 34.67x geomean speedup over CPU. Integrated into a prior ZKP accelerator at iso-area, it yields a 3.15x geomean speedup on end-to-end proof generation. The framework is open source on GitHub.
- Automatically generates ASIC and FPGA point-addition implementations for any supported elliptic curve equation form.
- 2.71x geomean speedup and 3.11x area reduction versus prior ASICs on 12nm node.
- 3.15x geomean speedup on end-to-end proof generation integrated into a prior ZKP accelerator.
- First comprehensive hardware-focused study spanning over 1,000 point-addition design points.
From the original article
1 min read at arxiv.orgZero-Knowledge Proofs (ZKPs) are critical for privacy-preserving and verifiable computation, but their cryptographic primitives impose high computational overheads. One such primitive is point addition (PADD) on elliptic curves.
By Gaurav Kuwar · arxiv.org
A short excerpt; the article and its images belong to the publisher. Summary, key facts and assessment above are AI-written from the article and can be wrong.