Search: “hardware-architecture”

New hardware device can RAM into encrypted memory, expose your data

Researchers built a $200 DDR5 interposer that silently drops memory writes to break TDX, SGX, and SEV-SNP confidential VM integrity, requiring physical access.

Researchers from KU Leuven, ETH Zurich, Durham University, and Google demonstrated DDRop, a hardware interposer costing under $200 that corrupts DDR5 bus commands to silently drop writes to encrypted memory, enabling replay attacks on confidential VMs. Because scalable memory encryption lacks freshness checks, protected VMs keep computing on stale attacker-selected data; on an Intel TDX server the attack forces debug mode for plaintext memory reads or forges attestation reports, succeeding in under two minutes without crashing. Intel and AMD both called the attack out of scope for their cloud threat models, with no mitigation planned, and proposed cache line versioning appears still vulnerable. The full interposer design is being released as open-source hardware.

The Register · Security·Sep 14, 18:31 UTC · 1d agoResearch

Anthropic's new hardware standard lets AI agents control the physical world

Anthropic announced a standardized hardware driver interface letting AI agents control physical devices and for devices to interoperate.

Anthropic introduced a new hardware standard that provides a standardized driver interface for AI agents to control the physical world. The standard aims to let devices communicate with AI systems and with each other. Details on adoption, partners, or specifications were not included in the available text.

Ars Technica · AI·Aug 27, 22:15 UTC · 19d agoAI industry1

How CHERIoT Provides Strong and Usable Isolation Without an MMU

ACM Queue paper explains how CHERIoT uses CHERI hardware capabilities to give microcontroller-class IoT devices memory and privilege isolation without an MMU.

The ACM Queue article (DOI 10.1145/3831361) describes CHERIoT, a RISC-V-derived platform that scales CHERI capability-based hardware down to small embedded and IoT microcontrollers. It provides strong, fine-grained isolation and memory safety without a memory management unit, aiming to make compartmentalization practical for low-cost devices. The piece emphasizes usability of the isolation model alongside its security guarantees.

Lobsters · security·Sep 10, 14:59 UTC · 6d agoResearch

Securing the Infrastructure of Intelligence

NVIDIA positions AI factories combining chips, networking, power and data as the defining infrastructure of the AI economy needing full-stack security.

NVIDIA's blog argues that AI factories are the defining infrastructure of the AI era, transforming energy and data into intelligence that powers businesses and countries. It frames compute as revenue and lists the full stack of critical resources required: advanced chips, packaging, memory, networking, land and power. The piece is a corporate positioning article about securing this infrastructure, with no specific incident or product announcement detailed in the excerpt.

NVIDIA Blog·Aug 17, 12:34 UTC · Aug 17, 2026AI industry

Speculative Decoding in vLLM on AMD GPUs

vLLM benchmarks speculative decoding on AMD Instinct MI300X and MI355X GPUs across five drafting methods including EAGLE-3 and native MTP.

The vLLM project documents draft-and-verify speculative decoding support for AMD GPUs via ROCm, comparing native MTP, Gemma 4 MTP, EAGLE-3, DFlash, and DSpark drafting approaches. Output-token throughput effects varied with drafting method, proposal length, model family, draft checkpoint, workload, and acceptance behavior. The post also covers how to enable each method plus practical tuning and observability considerations.

Hacker News · AI·Sep 7, 09:26 UTC · 9d agoAI tools & infraHN 141↑ · 52 comments1

Why Scaling AI Compute Performance Requires a New Power Architecture

NVIDIA argues AI factories need 800 VDC power distribution as dense GPU racks outgrow traditional AC-based delivery.

NVIDIA's blog contends each generation of accelerated computing demands higher rack density and more efficient, scalable power distribution. It frames the bottleneck as how power moves from the grid to the GPU rather than raw wattage, and describes limitations of traditional AC power delivery. NVIDIA advocates a new 800 VDC power architecture for AI factories.

NVIDIA Blog·Aug 11, 15:00 UTC · Aug 11, 2026AI industry

Retrospectively Reverse-Engineering Apple's Neural Engine

A developer reverse-engineers Apple's M1 Neural Engine architecture, mapping compute cores, MAC datapaths, and schedulers to explain the NPU's decline as transformers displaced CNN workloads.

A developer who previously maintained a reverse-engineered Linux driver for Apple's Neural Engine (ANE) published a retrospective deep dive mapping the M1 ANE's full internal architecture: compute, datapath, scheduler, memory, and execution model. The M1 ANE has 16 compute cores with 128 FP16 (or 256 INT8) MAC lanes each, totaling 2048 parallel MAC lanes, using 32-bit Q16.16 fixed-point accumulation with FP16 readout and an accumulator that saturates at 2^15. The author argues the ANE's dataflow was architected around the predictable reuse patterns of 2017-era CNN workloads (dating to the A11 Bionic), which autoregressive transformer decode broke, limiting its usefulness for general ML. With Apple's M5 folding ANE cores into GPU cores to tout LLM performance, the post frames this as the beginning of the end for the standalone NPU.

Hacker News · AI·Sep 12, 07:54 UTC · 4d agoAI researchHN 54↑ · 7 comments2

CHERI-D Reincarnate: efficient multicore CHERI temporal memory safety through allocation reincarnation (draft version)

CHERI-D Reincarnate adds allocation reincarnation to CHERI, quarantining generation IDs instead of memory to cut temporal memory-safety overheads on multicore systems.

The proposal extends CHERI-D temporal memory safety by quarantining exhausted generation IDs rather than memory slots, allowing freed memory immediate reuse through allocation reincarnation. It adds coherent ID caching and multicore support connecting physical coherence events to the virtually addressed ObjID buffer. The design was implemented as a hardware-software co-design across CHERI-Toooba FPGA softcore, QEMU, LLVM/Clang, and CheriBSD. Across evaluated workloads it substantially reduces memory-sweep frequency and quarantine overhead with low performance and hardware cost.

arXiv cs.CR·Sep 10, 14:19 UTC · 6d agoResearch

Delivering Vera: NVIDIA’s First CPU Built for Agents Is Shipping Now

NVIDIA's Vera CPU, its first processor built for AI agents, is now shipping at scale to partners across the AI ecosystem.

NVIDIA announced that Vera, its first CPU designed specifically for agentic AI workloads, has begun shipping at scale. Vice President of Hyperscale and HPC Ian Buck is hand-delivering early Vera CPU systems to organizations across the AI ecosystem, signaling full production availability of the data-center processor.

NVIDIA Blog·Aug 27, 13:00 UTC · 20d agoAI industry

FreqSpaNet: Frequency and Spatial Learning of SFPF for Physical Layer Hardware Integrity Detection

FreqSpaNet learns spatio-frequency polarization fingerprints to detect unauthorized wireless hardware replacement, reaching 96.31% mean AUROC across seven replacement scenarios.

FreqSpaNet is a representation learning network for open-set hardware anomaly detection using spatio-frequency polarization fingerprints (SFPFs), which capture device-dependent responses across frequencies and directions. A frequency branch models local variations among neighboring frequencies while a geometry-aware spatial branch models directional relationships via angular information, combined through adaptive fusion and complementary pretraining. It achieves a mean AUROC of 96.31%, 9.05 points above the baseline, and is verified under seven hardware replacement scenarios.

arXiv cs.AI / cs.LG / cs.CL·Sep 15, 17:32 UTC · 22h agoAI research

FOMO in the SOC: Where AI Platforms like Claude Actually Fit

The Hacker News·Aug 3, 11:30 UTC · Aug 3, 2026Malware

CertiFlash: A Formal Verification Framework for Flash Translation Layers in Computational Solid State Drives

CertiFlash provides machine-checked formal verification of SSD flash translation layers, proving isolation, integrity, and ownership invariants to prevent tenant data leaks.

CertiFlash is an open-source formal verification framework for Flash Translation Layers (FTL) in computational SSDs, mechanized in the Rocq proof assistant. It shows that a faulty FTL can corrupt device state at five surfaces (e.g., leaking data between tenants or dropping integrity tags), demonstrated on a DaisyPlus OpenSSD. Designers prove once that every operation of a general FTL model preserves a global invariant covering mapping, isolation, integrity, ownership, and allocation; new designs need only discharge five hypotheses. Across four case studies, added effort was 27-3,231 lines against a 16,489-line framework.

arXiv cs.CR·Sep 9, 15:44 UTC · 7d agoResearch1

Architecting memory and storage in the AI era

Analysis argues AI inference shifts data-center bottlenecks to memory and storage, urging balanced compute, memory, storage, and network architecture over raw compute.

MIT Technology Review, citing Tirias Research principal analyst Jim McGregor, argues that AI inference and agentic workloads make data movement the key constraint, elevating memory and storage from background hardware to strategic assets. The piece says RAG and real-time inference require continuous data retrieval and caching that legacy infrastructure cannot support. It frames infrastructure planning as a business decision balancing performance, efficiency, cost, and scalability in healthcare, finance, and customer-facing AI.

MIT Technology Review · AI·Sep 4, 18:39 UTC · 11d agoAI industry

Design Docs Are All You Need: An AI-native Machine-Learning Performance Tool

Researchers present SMART, an ML performance-modeling library regenerated by AI coding agents from natural-language design docs instead of code.

The paper describes SMART, a symbolic performance-modeling library whose main branch contains almost no code: the repository is a DAG of self-contained design documents, and coding sub-agents regenerate implementations from only the docs on version updates. Reliability rests on a worked-example doc style used as in-context demonstrations and a minimal operator IR with SymPy cost expressions, offering both fast analytical roll-up and fine-grained modulo-scheduling modes. Regenerated implementations reproduce hand-audited reference models, including DeepSeek-V3 serving on a TPU pod slice, to round-off precision.

arXiv cs.AI / cs.LG / cs.CL·Sep 4, 17:08 UTC · 11d agoAI research1

OPEN-1B: A Fully Auditable Training Run

Open-1B releases a 1B-parameter model with bitwise-reproducible training, letting independent auditors verify every step of the run on commodity hardware.

The paper introduces a 'fully auditable' tier of model transparency: every training operation is reproducible with bitwise certainty on heterogeneous commodity hardware by imposing definite ordering on GPU kernel reductions, data batch ordering, and collective communication. Because replaying a full run on one machine is infeasible, a collective verification scheme lets many independent auditors certify individual steps covering the whole run. The authors release Open-1B with its full pretraining dataset, every intermediate checkpoint, the training codebase, and an audit harness. This rules out undisclosed data, injected biases, or backdoors that proof-of-learning or proof-of-training-data techniques cannot exclude.

arXiv cs.AI / cs.LG / cs.CL·Sep 15, 16:23 UTC · 23h agoAI research

OptiPrime: Optimizing Private Inference through Protocol-Hardware Co-design

OptiPrime co-designs HE-MPC protocols with hardware acceleration to remove network communication bottlenecks in private DNN inference, beating Cheetah by up to 5.7x.

OptiPrime is a protocol-hardware co-optimization framework for private deep neural network inference based on hybrid homomorphic encryption (HE) and multi-party computation (MPC). It introduces a novel HE protocol for convolutions that reduces the number of transmitted output ciphertexts, addressing the network bottleneck that limits gains from commercial HE accelerators. A lightweight compression system reduces weight plaintext memory traffic by 10x, while a specialized dataflow maximizes on-chip reuse of intermediate ciphertexts. Experiments show up to 5.7x speedup over the Cheetah baseline on CPUs and 4.2x with an accelerator.

arXiv cs.CR·Sep 15, 09:29 UTC · 1d agoResearch

Arm Mali G2-Ultra NX GPU: desktop-class mobile gameplay with AI-native graphics

Arm unveiled Mali G2-Ultra NX, its first AI-native mobile GPU with in-shader neural acceleration, third-gen ray tracing, and up to 24% higher benchmark performance.

Arm announced the Mali G2-Ultra NX, the first AI-native Mali GPU, integrating neural accelerators directly into shader cores alongside a new execution engine and third-generation hardware ray tracing. It introduces Neural Super Sampling (NSS), Neural Frame Rate Upscaling (NFRU), and Neural Super Sampling and Denoising (NSSD); the Neural Dawn demo with Sumo Digital showed up to 4x performance efficiency and 70% lower external memory traffic versus native rendering. Arm claims up to 24% higher benchmark performance, 13% lower DRAM traffic on ray tracing benchmarks, and up to 120 FPS with NFRU. Over 14 billion Mali GPUs have shipped to date.

Hacker News · AI·Sep 8, 04:06 UTC · 8d agoAI industryHN 71↑ · 53 comments1

Wazuh and AI For Enhanced SOC Workflows

Wazuh details AI-powered SOC workflows via its AI Analyst, self-hosted Llama 3 via Ollama, and Claude 3.5 Haiku integrations.

Wazuh outlines how AI can augment SOC analysts handling high alert volumes. The Wazuh AI Analyst on Wazuh Cloud uses Amazon Bedrock and Anthropic Claude to generate scheduled security posture reports. Self-hosted options include Llama 3 with Ollama, FAISS, and LangChain for privacy-sensitive threat hunting, plus an OpenSearch Assistant integration with Claude 3.5 Haiku. This is a vendor-contributed piece describing product capabilities rather than an incident or vulnerability.

The Hacker News·Aug 21, 11:21 UTC · 26d agoTools

SCHERI: Provably Secure Speculation Under the Constant-Time Policy for CHERI (Extended Version)

Researchers formally prove existing CHERI speculation proposals leak secrets and present SCHERI, a processor design with end-to-end Spectre-resistant constant-time guarantees.

The paper builds a formal framework reasoning jointly about capability safety, speculative execution, and information-flow security on CHERI architectures. It demonstrates that existing secure-speculation proposals fail to preserve constant-time confidentiality guarantees and can transiently leak isolated secrets. The authors present SCHERI, a new processor design formally proven to provide end-to-end secure speculation for the constant-time policy, resilient to Spectre attacks.

arXiv cs.CR·Sep 15, 16:33 UTC · 23h agoResearch

Linux Foundation takes on TRACE, a hardware-backed runtime evidence specification for AI agents

The Linux Foundation adopts TRACE, an OPAQUE-contributed spec giving AI agents hardware-attested, cryptographically verifiable runtime and compliance evidence.

The Linux Foundation accepted the TRACE (Trust, Runtime Attestation and Compliance Evidence) specification contributed by OPAQUE, developed with AMD, Intel, Microsoft, and the Technology Innovation Institute. TRACE binds runtime environment, software, policies, data classifications, and tool usage into a portable, cryptographically verifiable artifact, composing existing standards such as RATS, EAT, SLSA, SCITT, SPIFFE, and EAR. It recorded nearly 135,000 PyPI downloads within 10 weeks of its June 2026 introduction, and its technical workstream will be hosted by the Coalition for Secure AI.

Help Net Security·Aug 26, 00:00 UTC · 21d agoAI tools & infra

Φ-Bench: Can Large Language Models Engineer the Infrastructure That Powers Them?

Researchers release Phi-Bench, a benchmark evaluating frontier LLMs on open-ended, long-horizon engineering and optimization of the LLM infrastructure stack.

Phi-Bench evaluates LLMs on open-ended engineering of the LLM infrastructure stack, derived from optimization problems studied in frontier research and grounded in real-world code repositories. Tasks range from localized kernel-level function completion to long-horizon implementation and end-to-end system optimization. Experiments on frontier LLMs reveal current capabilities and limitations on the path toward autonomous optimization of future AI infrastructure.

Hugging Face daily papers·Sep 8, 20:00 UTC · 7d agoAI research1

MicroHasTEE: Bare-Metal Haskell for Type-Level Peripheral Ownership on Armv8-M

MicroHasTEE expresses TrustZone secure and non-secure firmware as one typed Haskell program, catching peripheral-ownership inconsistencies at compile time.

MicroHasTEE is a multiparty Haskell framework that models both TrustZone firmware images as participants in a single typed program, using type-level capability ledgers to track peripheral acquisition, configuration, transfer, and finalization. MicroHs compiles the shared program twice to produce separate bare-metal Secure and Non-secure firmware images. The framework rejects inconsistent resource use, post-configuration attribution changes, wrong-domain callbacks, and calls to unregistered Secure services. A door-lock case study on an STM32U5 Nucleo board produced images of 232.7 KiB and 228.4 KiB of flash with roughly 220 KiB of SRAM per domain.

arXiv cs.CR·Sep 11, 08:34 UTC · 5d agoResearch1

Hardware Fingerprinting FTQC via Quantum Decoder Timing

Quantum decoder timing on IBM Heron processors forms a side channel enabling device fingerprinting with 89% accuracy and workload inference.

The work demonstrates that wall-clock syndrome-decoding times on fault-tolerant quantum computers constitute a novel hardware side channel. Using per-shot decoder timings from three IBM Heron processors collected over 68 days, a passive observer can reconstruct detector-firing distributions, estimate logical error rate, infer code distance, and fingerprint the specific device with up to 89% accuracy versus 33% for random guessing. Noisy simulation based on Google's 105-qubit Willow processor distinguishes nine surface-code patches at 81% accuracy, showing the channel persists across vendors and code families.

arXiv cs.CR·Sep 10, 19:24 UTC · 5d agoResearch

The Agentic SOC – From AI Theater to Real Defense

Recorded Future and Accenture experts outline how security teams can move beyond 'AI theater' toward agentic SOC operations guided by measurable KPIs.

Recorded Future published a blog featuring perspectives from its own and Accenture experts on building an agentic security operations center. The piece argues organizations should prioritize measurable KPIs and proactively mitigate risks from autonomous agents. It also discusses evolving the analyst role from managing alerts to managing agents.

Recorded Future·Sep 1, 00:00 UTC · 15d agoIndustry

[hardware] Fullhan FH8626V100 - Multiple Vulnerabilities

Multiple vulnerabilities in the Fullhan FH8626V100 hardware chip have been disclosed alongside public proof-of-concept exploits.

Exploit-DB lists an entry covering multiple vulnerabilities in the Fullhan FH8626V100, a hardware component. The listing provides no CVE ids, vulnerability classes, or evidence of in-the-wild exploitation. Impact is likely limited to devices embedding the affected chip.

Exploit-DB·Sep 2, 00:00 UTC · 14d agoExploit / PoC

Graph Machine: Towards Better Pretraining via Edges

Researchers propose Graph Machine, an O(n)-state sparse architecture that replaces 75% of Qwen3-0.6B dense layers with only slight loss change.

The paper introduces the Graph Machine (GM), an architecture that maintains an O(n)-sized state accessed through sparse, dynamic routing via pointer-like edges updated differentiably by a referral mechanism resembling pointer chasing. The authors replaced 75% of dense Transformer layers in Qwen3-0.6B with GM sparse layers and pretrained from scratch on 15.7B tokens. Retrieving 2 of 4,096 tokens per KV head in each sparse layer degrades loss only slightly, while retrieving 4 marginally improves loss over the dense baseline.

Hugging Face daily papers·Sep 1, 20:00 UTC · 14d agoAI research

Understanding the Security Boundary of Obfuscation-based On-Device LLM Protection

Researchers formalize obfuscation primitives for TEE-protected on-device LLMs and show a Collapse attack breaks ArrowCloak, TSQP, and LoRO, then extend the boundary.

The paper formalizes obfuscation primitives for TEE-Shielded LLM Partition (TSLP) schemes that offload computationally intensive layers from a Trusted Execution Environment to external GPUs. A novel primitive-guided attack, Collapse, demonstrates a shared vulnerability in prominent published methods including ArrowCloak (Security'25), TSQP (S&P'25), and LoRO (NeurIPS'25). The authors then introduce two new obfuscation primitives and integrate them with existing constructs to formulate an extended security boundary (O_ext).

arXiv cs.CR·Sep 9, 12:51 UTC · 7d agoAI safety & security

Memory-Efficient Designs for Word-Wise Universal Fully Homomorphic Encryption

BXT framework mitigates FHE memory bottlenecks via ciphertext compression, serialization, delayed seeding, and digit pruning, achieving up to 3.8x CNN inference speedup.

A new paper proposes BXT, an optimization framework for word-wise Universal Fully Homomorphic Encryption that targets the memory bottleneck rather than compute. It combines four techniques: ciphertext compression via seed regeneration, bit-packed ciphertext serialization for L2-to-L1 transfers, delayed PRNG-heavy offline seed generation across aggregated operations, and fault-aware ciphertext digit pruning. On CNN inference, the BXT-CSO50 configuration achieves up to 3.8x speedup over a 100x GPU baseline with under 1% accuracy loss at 50% comparison precision.

arXiv cs.CR·Sep 4, 06:03 UTC · 12d agoResearch

Cortex Cloud Archives

Palo Alto Networks publishes a product category page for Cortex Cloud, an AI and automation platform for cloud and SOC workflows.

This item is a product category archive page for Palo Alto Networks' Cortex Cloud, describing it as an AI and automation-driven platform spanning code to cloud to SOC. The page contains no new research, incident, or product release details beyond marketing language about prioritizing risks and accelerating remediation.

Palo Alto Unit 42·Aug 20, 19:01 UTC · 26d agoIndustry

Powering AI is an architecture problem

Sponsored analysis argues AI data centers need medium-voltage, inline power architecture after Virginia grid faults knocked over 3GW of load offline.

A sponsored MIT Technology Review piece recounts a July 22, 2026 transmission fault in Ashburn, Virginia that shed more than 3 GW of data center load, and a 2024 incident where one failed surge arrester dropped about 60 facilities and 1,500 MW. It argues legacy UPS-based power stacks fail at AI scale because campuses can swing 70% of load in milliseconds and trip offline during grid disturbances. The proposed fix moves protection to medium voltage (13.8 kV and above) in inline enclosures near substations, improving density, permitting timelines, and backup power economics. A full-scale system tested at the DOE National Laboratory of the Rockies cleared ERCOT large-load ride-through requirements.

MIT Technology Review · AI·Sep 10, 11:00 UTC · 6d agoAI industry1