FASTAR: FRI Accelerator for Scalable Transparent ARguments of Knowledge
FASTAR is an FPGA accelerator that speeds the FRI protocol used by transparent post-quantum zk-STARKs.
FASTAR is an FPGA accelerator for the FRI protocol that dominates prover cost in transparent zk-STARK systems. Unlike Groth16-style zk-SNARKs, these proofs rely only on collision-resistant hashes and avoid a trusted setup, but FRI creates heavy Merkle commitments and irregular memory access. Implemented with High-Level Synthesis, FASTAR parameterizes polynomial evaluation, recursive split-and-fold, and Merkle-tree construction and generates designs from a board's resource constraints.
- FASTAR accelerates FRI, the main prover bottleneck in zk-STARKs.
- It uses HLS blocks for evaluation, split-and-fold, and Merkle trees.
- Hardware is generated from a target FPGA's resource and memory limits.
- The design targets transparent, hash-based, post-quantum proofs.
Full article211 words · extracted from arxiv.org · click to collapse
Zero-Knowledge Proofs (ZKPs) enable a prover to cryptographically convince a verifier of the validity of a statement without revealing any underlying secrets, forming a foundational primitive for verifiable computation. The ZKP landscape is undergoing a fundamental shift from classic zk-SNARKs such as Groth16, which rely on trusted setup and are vulnerable to quantum adversaries, toward transparent, post-quantum constructions such as zk-STARK. These systems achieve post-quantum security by relying solely on collision-resistant hash functions, however, at the cost of substantial computational overhead. In particular, the Fast Reed--Solomon Interactive Oracle Proof of Proximity (FRI) protocol dominates prover complexity, generating massive data volumes, repeated Merkle-tree commitments, and irregular memory access patterns that limit performance and energy efficiency on general-purpose processors. To address these challenges, this work proposes FASTAR, a novel FPGA-based accelerator for the FRI protocol. Unlike accelerators that pursue fixed high-performance kernels on expensive ASIC process nodes, FASTAR adopts a constraint-driven design methodology. Our framework is implemented with High-Level Synthesis (HLS) and composed of fully parameterizable building blocks for the major stages of FRI, including polynomial evaluation, recursive split-and-fold, and Merkle-tree construction. From user-provided board specifications, FASTAR automatically generates hardware implementations tailored to the resource and memory constraints of the target FPGA, enabling deployment across a wide range of platforms without manual redesign.
Text extracted automatically; images, tables and formatting may be missing. Original: https://arxiv.org/abs/2609.25535