SensorGuard-RV protects sensor data on RISC-V devices
SensorGuard-RV delivers protected samples to registers in 51.9 μs using hardware encryption.
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Stories tagged #fpga
arXiv toolchain enables AWS FPGA ML development with Vitis HLS
The paper presents a complete Vitis HLS to HDK bridge for academic FPGA development on AWS EC2 F2 infrastructure.
HDPU Enables Neural Decisions at Sensor on FPGA
The HDPU processes frames on Artix-7 FPGA and spares the host all inference.
End-to-end NTT on FPGA accelerates FHE operations
The design transforms 2^16 coefficients every 5.12 μs at 400 MHz and accelerates FHE by 1.8-2.2x.
arXiv evaluates randomized caches for side-channel protection
FPGA implementation of four randomized cache designs in a multi-core RISC-V SoC shows pipelining alone insufficient and redesign needed to limit frequency loss to 10% below baseline.
Study tests black-box watermarks for hyperdimensional classifiers
AdaptHD and OnlineHD kept verification at 1% trigger exposure with at most 0.58 points of mean accuracy loss.
Power, Performance, and Area of HPC-Based Malware Detectors: An FPGA and Open-PDK ASIC Study
FPGA and ASIC study finds tree-based HPC malware detectors use far less area and energy than function-based models.
Secure Aggregate Encryption with Identity-Based Authentication for Multi-Vendor FPGA Cloud Deployment
Researchers present SAEID, a pairing-based framework that authenticates FPGA devices and protects multi-vendor cloud bitstreams.
Efficient HQC Implementations on RISC-V: A Cross-Layer Design Space Exploration
A 29,920-configuration RISC-V study finds faster, smaller HQC implementations on FPGA.
The Achilles' Heel of Partial Reconfiguration: Optical Side-Channel Leakage on the 7-Series ICAP
Researchers recover plaintext FPGA configuration from AMD 7-Series ICAP using optical probing during partial reconfiguration.
Application Agnostic EM Side-Channel Emanations of the FPGA Clock Distribution Network
FPGA electromagnetic leakage rose about 1.3 times when clock-resource use increased from 25% to 90%.
Peregrino: A Full-Hardware Accelerator for the Complete Falcon Post-Quantum Digital Signature Scheme on Resource-Constrained Edge Devices
Peregrino is a full HDL Falcon accelerator that fits NIST Falcon-1024 on one Artix-7 FPGA.
SADRA: Sound Capability-based Access Control System for Resource-Disaggregated Architectures
SADRA enforces SmartNIC capability checks for disaggregated resources at 89.5 Gbit/s with immediate revocation.
BenX: Resource-Sharing Permutations for Computational Integrity
BenX, a new permutation hash, matches Poseidon2 FPGA throughput while improving hardware sharing and some zero-knowledge proving costs.
FASTAR: FRI Accelerator for Scalable Transparent ARguments of Knowledge
FASTAR is an FPGA accelerator that speeds the FRI protocol used by transparent post-quantum zk-STARKs.
TERMon: Detecting Persistent Behavioral Threats in Edge AI via Hardware-Native Ternary Runtime Monitor
TERMon, an FPGA runtime monitor, flags harmful weight corruption in edge AI using ternary behavioral fingerprints.
Locus: A Framework for Exploring and Optimizing Point Addition Hardware for Zero-Knowledge Proofs
Locus framework automates ASIC and FPGA point-addition designs for elliptic curves, achieving 2.71x speedups and 3.11x area reductions for ZKPs.
CHERI-D Reincarnate: efficient multicore CHERI temporal memory safety through allocation reincarnation (draft version)
CHERI-D Reincarnate adds allocation reincarnation to CHERI, quarantining generation IDs instead of memory to cut temporal memory-safety overheads on multicore systems.
Chypothermia: Clock Freezing for Static Side-channel Attacks
Chypothermia attack uses cryogenic cooling to disable clock and voltage sensors, evading detection and blocking key zeroization on OpenTitan root of trust.
Deep Learning-Based Detection of Electrical Faults and Power Quality Disturbances in Aerospace Power Systems
Compact ResNet detects electrical faults in 400 Hz aircraft power systems with 95.87 percent accuracy after deployment on Xilinx Zynq MPSoC.