Qwenputer compiles a RISC-V CPU into Qwen 3.5 4B weights
Original title: Qwenputer: A functioning, deterministic RISC-V CPU inside Qwen3.5
The experimental release treats Gated DeltaNet state as exact RAM and executes C and MicroPython during forward passes.
A researcher released Qwenputer, a stock Qwen 3.5 4B with extra layers that implement a 32-bit RISC-V core. The core uses Gated DeltaNet heads as addressable memory and runs as the model generates instruction-trace tokens. The author says it passes official riscv-tests, matches qemu, and ran 18 million instructions without error. Weights are on Hugging Face and ModelScope; code is on GitHub.
Unconfirmed: Correctness and the 18 million error-free instructions are the author's claims; the post is truncated.
- The CPU is RV32IM plus Zba and a small bignum unit.
- It occupies 11 layers in front of Qwen's 32.
- Qwen's original weights are unchanged; computer weights are added.
- A driver named RvChat loads firmware into Gated DeltaNet state.
- No training is used; a compiler writes the weights directly.
From the original article
9 min read at divagr.com
A stock Qwen 3. 5 4B with a RISC-V CPU compiled into its weights, running on its own Gated DeltaNet layers as RAM. Qwenputer is a pretty fun experimental model.
By csmantle · divagr.com
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