RISC-V MCU design bounds runtime protection-policy delegation
A CVA6-based World Checker adds 7.1% LUT and 1.2% FF for eight rules, with no access-latency or frequency loss.
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Stories tagged #risc-v
SensorGuard-RV protects sensor data on RISC-V devices
SensorGuard-RV delivers protected samples to registers in 51.9 μs using hardware encryption.
arXiv evaluates randomized caches for side-channel protection
FPGA implementation of four randomized cache designs in a multi-core RISC-V SoC shows pipelining alone insufficient and redesign needed to limit frequency loss to 10% below baseline.
RV2GC rebuilds garbling around fixed RISC-V instruction circuits
On nine benchmarks, ARM2GC-to-RV2GC runtime ratios ranged from 12.81 to 4,043, with public scheduling kept outside the circuits.
Qwenputer compiles a RISC-V CPU into Qwen 3.5 4B weights
The experimental release treats Gated DeltaNet state as exact RAM and executes C and MicroPython during forward passes.
SecDMP stops data-memory prefetcher leakage at low cost
Marked secrets stay out of the prefetcher; with speculative defenses, constant-time code is fully protected.
Anthropic says Claude proved properties in 123 open-source libraries
Proofs cover single-threaded RISC-V static binaries and inputs under 64 MB; a subset and a Claude skill are being published.
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FreeSBee: A Constant-Time Compilation Pipeline
FreeSBee hardens compiler output against timing side channels using taint analysis and control-flow transforms.
We Query, Therefore We Compute: On Oracle Computation beyond the Machine, with an Application to Agents
A two-stack oracle machine unifies LLM workflows and agents, with ArchNights proposed on RISC-V.
Efficient HQC Implementations on RISC-V: A Cross-Layer Design Space Exploration
A 29,920-configuration RISC-V study finds faster, smaller HQC implementations on FPGA.
USN-8853-1: OpenSBI vulnerability
Ubuntu patched an OpenSBI flaw that can let attackers cause a denial of service.
Efficient TCitH-Based Alternatives to SLH-DSA: Cross-Layer ASIC Design of Mirath
A 22nm Mirath ASIC signs 17.8x faster than same-node SLH-DSA while using 58% less area.
How CHERIoT Provides Strong and Usable Isolation Without an MMU
ACM Queue paper explains how CHERIoT uses CHERI hardware capabilities to give microcontroller-class IoT devices memory and privilege isolation without an MMU.
AutoTrans: AI-Assisted Automatic Translation of Security Assertions for RISC-V Processors
AutoTrans uses LLMs with regex extraction and formal verification to automatically translate security assertions across RISC-V processors, achieving 78% unattended acceptance.