arXiv toolchain enables AWS FPGA ML development with Vitis HLS
Original title: Enabling AWS Cloud FPGA Development Using High-Level Vitis HLS
The paper presents a complete Vitis HLS to HDK bridge for academic FPGA development on AWS EC2 F2 infrastructure.
We present a toolchain for development of ML models on AWS EC2 F2 cloud FPGA infrastructure from high-level language, implementing a complete Vitis HLS to HDK bridge to AFI workflow. A four-level methodology aids in localizing errors, including FPGA-specific circuit errors. The tools allow coding agents to implement FPGA designs from user directions. Deployment workflow, timing closure strategies, and practical HLS engineering decisions are documented. Validation uses TinyBERT fine-tuned for address Named Entity Recognition.
- Four-level methodology for error localization
- Complete Vitis HLS to HDK bridge
- Streams weights from host DRAM
- Poor performance vs CPU/GPU discussed
- Enables academic development on AWS FPGA
From the original article
1 min read at arxiv.orgWe present a toolchain for development of ML models on AWS EC2 F2 cloud FPGA infrastructure from high-level language, implementing a complete Vitis HLS to HDK bridge to AFI workflow that has been absent from the academic literature despite eight years of AWS FPGA availability.
By David Rostcheck · arxiv.org
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