Search: “memory-chips”

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New DDRop Attack Breaks Intel TDX and AMD SEV-SNP Confidential Computing

DDRop uses a sub-$200 DDR5 interposer to drop memory writes, breaking Intel TDX and AMD SEV-SNP confidentiality guarantees.

Researchers at KU Leuven, ETH Zurich, Durham University, and Google will present DDRop at ACM CCS 2026, a first active interposer attack on DDR5 that silently drops memory writes so processors keep reading stale encrypted data, exploiting the missing freshness guarantee in Intel TDX, Intel Scalable SGX, and AMD SEV-SNP. On Intel TDX's default logical integrity mode it enabled reading victim VM memory, toggling debug mode, and forging remote attestation; AMD SEV-SNP was limited to copying pages between VMs. TDX's stronger cryptographic integrity blocks cross-VM attacks but likely not attestation forgery. The team will release board designs, firmware, and attack code on GitHub; no evidence of real-world use exists and no simple patch is available.

The Hacker News·updated Sep 15, 09:57 UTC · 1d ago·first Sep 14, 16:58 UTC · 2d agoResearch 2 sources

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New hardware device can RAM into encrypted memory, expose your data

Researchers built a $200 DDR5 interposer that silently drops memory writes to break TDX, SGX, and SEV-SNP confidential VM integrity, requiring physical access.

Researchers from KU Leuven, ETH Zurich, Durham University, and Google demonstrated DDRop, a hardware interposer costing under $200 that corrupts DDR5 bus commands to silently drop writes to encrypted memory, enabling replay attacks on confidential VMs. Because scalable memory encryption lacks freshness checks, protected VMs keep computing on stale attacker-selected data; on an Intel TDX server the attack forces debug mode for plaintext memory reads or forges attestation reports, succeeding in under two minutes without crashing. Intel and AMD both called the attack out of scope for their cloud threat models, with no mitigation planned, and proposed cache line versioning appears still vulnerable. The full interposer design is being released as open-source hardware.

The Register · Security·Sep 14, 18:31 UTC · 2d agoResearch

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CHERI-D Reincarnate: efficient multicore CHERI temporal memory safety through allocation reincarnation (draft version)

CHERI-D Reincarnate adds allocation reincarnation to CHERI, quarantining generation IDs instead of memory to cut temporal memory-safety overheads on multicore systems.

The proposal extends CHERI-D temporal memory safety by quarantining exhausted generation IDs rather than memory slots, allowing freed memory immediate reuse through allocation reincarnation. It adds coherent ID caching and multicore support connecting physical coherence events to the virtually addressed ObjID buffer. The design was implemented as a hardware-software co-design across CHERI-Toooba FPGA softcore, QEMU, LLVM/Clang, and CheriBSD. Across evaluated workloads it substantially reduces memory-sweep frequency and quarantine overhead with low performance and hardware cost.

arXiv cs.CR·Sep 10, 14:19 UTC · 6d agoResearch

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Windows 11’s strongest security defenses can be bypassed without a screwdriver

Researchers found a script-only attack, 'Download More RAM', that rewrites DIMM configuration chips to bypass Windows 11 VBS and HVCI security boundaries.

Researchers at the University of Birmingham and Durham University showed that overwriting configuration data on unprotected DDR4/DDR5 module chips creates memory aliases that let attackers with existing privileged access defeat Virtualisation-based Security and HVCI, re-enable blocklisted drivers, kill EDR, and bypass group policy. Microsoft assigned CVE-2026-23670 and shipped mitigations in its April 2026 updates; systems with Secure Boot enabled are protected. Affected unprotected product lines are estimated at more than half of the high-performance consumer memory market and over 70% of the gaming segment.

Help Net Security·Aug 17, 00:00 UTC · Aug 17, 2026VulnerabilityCVE-2026-236701

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DDRop Attack Forces Intel TDX Confidential VMs Into Debug Mode and Exposes Memory

KU Leuven and ETH Zurich researchers released DDRop PoC hardware that forces Intel TDX confidential VMs into debug mode and exposes plaintext memory.

Researchers from KU Leuven, ETH Zurich, Google, and Durham University published proof-of-concept code, hardware designs, and firmware for DDRop, a DDR5 interposer that injects parity errors to drop selected cache-line writebacks. Because Intel TDX, Intel Scalable SGX, and AMD SEV-SNP lack per-line cryptographic freshness, processors decrypt and accept stale DRAM contents as current state. The PoC flips a victim's ATTRIBUTES.DEBUG flag to enable TDX debug mode, then copies victim memory in plaintext and can forge attestation reports. Affected environments include Intel 5th- and 6th-generation Xeon Scalable with TDX; Intel says the attack falls outside its cloud-computing threat model.

GBHackers·Sep 15, 09:57 UTC · 1d agoResearch

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SK Hynix reportedly in talks with Intel to build memory chips in US

SK Hynix is reportedly negotiating with Intel to manufacture memory chips in the US, possibly leasing space at Intel's Ohio fab.

Reuters reports SK Hynix and Intel have discussed SK Hynix producing RAM in the US for the first time, including leasing space at Intel's planned Ohio factory or forming a joint venture that could include cloud-service providers; SK Hynix says nothing is finalized. The company is already building a $3.8 billion AI chip packaging and research facility in West Lafayette, Indiana, with mass production expected to begin in 2029, amid surging HBM demand from AI data centers. The potential deal could face a South Korean government review over transfers of strategically important chip technology, and follows Intel's 2020 sale of its NAND flash business to SK Hynix for $9 billion.

TechCrunch · AI·13:23 UTC · 10h agoAI industry

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Memory-Efficient Designs for Word-Wise Universal Fully Homomorphic Encryption

BXT framework mitigates FHE memory bottlenecks via ciphertext compression, serialization, delayed seeding, and digit pruning, achieving up to 3.8x CNN inference speedup.

A new paper proposes BXT, an optimization framework for word-wise Universal Fully Homomorphic Encryption that targets the memory bottleneck rather than compute. It combines four techniques: ciphertext compression via seed regeneration, bit-packed ciphertext serialization for L2-to-L1 transfers, delayed PRNG-heavy offline seed generation across aggregated operations, and fault-aware ciphertext digit pruning. On CNN inference, the BXT-CSO50 configuration achieves up to 3.8x speedup over a 100x GPU baseline with under 1% accuracy loss at 50% comparison precision.

arXiv cs.CR·Sep 4, 06:03 UTC · 12d agoResearch

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MeClear: Cooperative Game-Theoretic Attribution and Risk-Aware Memory Clearance for Long-Horizon LLM Agents

MeClear uses cooperative Shapley attribution to clear harmful memories from long-horizon LLM agents, boosting task recovery by 25.5 points over baselines.

The paper introduces MeClear, a task-conditioned memory clearance framework for long-horizon LLM agents that identifies and selectively suppresses memories with negative downstream utility without permanently altering the persistent memory bank. It combines Leave-One-Out screening with sampled cooperative Shapley attribution to distribute utility across interacting evidence, resolving redundant conflict masking that single-removal evaluations miss. Across ten long dialogue memory pools it achieves 85.9% target recall and 82.3% overall task recovery, a 25.5 percentage-point improvement over LOO baselines.

arXiv cs.AI / cs.LG / cs.CL·Sep 8, 17:46 UTC · 8d agoAI research

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SimpleMemVLA: A Simple but Effective Native-Video Memory for Vision-Language-Action Models

SimpleMemVLA passes full timestamped video history straight to a VLA backbone, setting state of the art on four memory benchmarks.

SimpleMemVLA is a vision-language-action model for long-horizon manipulation that removes the dedicated memory module entirely. It keeps sampled history intact and feeds it to the backbone as timestamped video, with the hidden states of a generated sub-task serving as the only channel into a standard flow-matching action head. Prefilling the shared history prefix during action execution keeps latency close to a single-frame VLA. The system sets a new state of the art on four memory benchmarks and outperforms retrieval, compression and recurrent-state mechanisms, with causal interventions confirming the policy genuinely reads its history.

Hugging Face daily papers·Sep 1, 20:00 UTC · 15d agoAI research

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How CHERIoT Provides Strong and Usable Isolation Without an MMU

ACM Queue paper explains how CHERIoT uses CHERI hardware capabilities to give microcontroller-class IoT devices memory and privilege isolation without an MMU.

The ACM Queue article (DOI 10.1145/3831361) describes CHERIoT, a RISC-V-derived platform that scales CHERI capability-based hardware down to small embedded and IoT microcontrollers. It provides strong, fine-grained isolation and memory safety without a memory management unit, aiming to make compartmentalization practical for low-cost devices. The piece emphasizes usability of the isolation model alongside its security guarantees.

Lobsters · security·Sep 10, 14:59 UTC · 6d agoResearch

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MemSentry: A Framework for Detecting Persistent Memory Poisoning in Agentic AI

MemSentry intercepts persistent-memory writes in agentic AI to catch memory poisoning, reaching 91.7% accuracy with SBERT+LR classification.

Memory poisoning lets adversaries plant crafted content in an agent's long-term memory to suppress security alerts, enable privilege escalation, or override policies without modifying model weights or system prompts. The paper presents MemSentry, a configuration-driven framework that evaluates proposed persistent-memory writes on source trust, semantic risk, attack radius over a dependency DAG, access risk, and a signed security-state delta to issue deterministic Accept, Review, or Quarantine decisions. Across 1,000 GPT-4-generated scenarios on a 20-asset dependency DAG, SBERT+LR achieved 91.7% accuracy and 0.908 macro-F1, all four classifiers detected 100% of external quarantine-class threats, and verified-insider writes are escalated for human review rather than auto-quarantined.

arXiv cs.CR·Sep 8, 13:40 UTC · 8d agoAI safety & security

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Bias-Induced Crossover in Absolute Capacity of Dense Associative Memory

Analysis shows biased patterns cut dense associative memory capacity from N^(n-1)/ln N to O(N^(n/2)), with a bias-induced crossover.

The paper analyzes dense associative memory capacity for biased centered binary patterns under the Krotov-Hopfield single-site criterion. Unbiased patterns (q=1/2) with order-n polynomial interactions yield capacity of order N^(n-1)/ln N, while fixed bias q<1/2 reduces capacity to O(N^(n/2)) for even n>=4 and O(N^((n+1)/2)) for odd n>=5. A bias-dependent crosstalk mean destabilizes sites carrying the frequent value, and an activity-dependent control potential restores the higher capacity within the conditioned-Gaussian approximation.

arXiv cs.AI / cs.LG / cs.CL·Sep 15, 17:16 UTC · 1d agoAI research

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Hardware Fingerprinting FTQC via Quantum Decoder Timing

Quantum decoder timing on IBM Heron processors forms a side channel enabling device fingerprinting with 89% accuracy and workload inference.

The work demonstrates that wall-clock syndrome-decoding times on fault-tolerant quantum computers constitute a novel hardware side channel. Using per-shot decoder timings from three IBM Heron processors collected over 68 days, a passive observer can reconstruct detector-firing distributions, estimate logical error rate, infer code distance, and fingerprint the specific device with up to 89% accuracy versus 33% for random guessing. Noisy simulation based on Google's 105-qubit Willow processor distinguishes nine surface-code patches at 81% accuracy, showing the channel persists across vendors and code families.

arXiv cs.CR·Sep 10, 19:24 UTC · 6d agoResearch

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Fortunate Recall: Ontology-Driven Memory Lifecycle Management for Persistent Coherence in LLMs

Fortunate Recall introduces ontology-based lifecycle policies for LLM memory, cutting confabulation roughly in half (e.g., 45.1% to 22.4%) versus Mem0.

Fortunate Recall (FR) is a composable policy layer that classifies personal facts into a 10+1 behavioral ontology and applies category-specific lifecycle rules including differential temporal decay, slot-key supersession, event-time validity, and retrieval routing. FR-Bank scores 76.9% on the new 516-question LifecycleBench, ahead of Mem0, A-MEM, Memory-R1, and MemoryOS (61%-70.5%), and 75.2% on LongMemEval-S. End-to-end, confabulation drops from Mem0's 45.1% to 22.4% over answered queries, with the ranking replicating on open-weight Kimi K2.5 and transferring to the independent BEAM benchmark (46.8% vs 32.9%).

arXiv cs.AI / cs.LG / cs.CL·Sep 9, 16:31 UTC · 7d agoAI research

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Speculative Decoding in vLLM on AMD GPUs

vLLM benchmarks speculative decoding on AMD Instinct MI300X and MI355X GPUs across five drafting methods including EAGLE-3 and native MTP.

The vLLM project documents draft-and-verify speculative decoding support for AMD GPUs via ROCm, comparing native MTP, Gemma 4 MTP, EAGLE-3, DFlash, and DSpark drafting approaches. Output-token throughput effects varied with drafting method, proposal length, model family, draft checkpoint, workload, and acceptance behavior. The post also covers how to enable each method plus practical tuning and observability considerations.

Hacker News · AI·Sep 7, 09:26 UTC · 9d agoAI tools & infraHN 141↑ · 52 comments1

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SCHERI: Provably Secure Speculation Under the Constant-Time Policy for CHERI (Extended Version)

Researchers formally prove existing CHERI speculation proposals leak secrets and present SCHERI, a processor design with end-to-end Spectre-resistant constant-time guarantees.

The paper builds a formal framework reasoning jointly about capability safety, speculative execution, and information-flow security on CHERI architectures. It demonstrates that existing secure-speculation proposals fail to preserve constant-time confidentiality guarantees and can transiently leak isolated secrets. The authors present SCHERI, a new processor design formally proven to provide end-to-end secure speculation for the constant-time policy, resilient to Spectre attacks.

arXiv cs.CR·Sep 15, 16:33 UTC · 1d agoResearch

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Memory-safety defects in the upstream (abandoned) AOSP OpenCORE AAC decoder, shipped unpatched by Samsung TizenRT

Abandoned AOSP OpenCORE AAC decoder has out-of-bounds-write and wild-pointer flaws reachable from attacker-controlled frames, unpatched in Samsung TizenRT.

The OpenCORE AAC decoder in AOSP's abandoned external/opencore tree contains memory-safety defects of the out-of-bounds-write and wild-pointer class. The code is still vendored and built by multiple projects, most notably Samsung's widely deployed TizenRT embedded RTOS. The defects are reachable from untrusted media because an AAC frame is attacker-controlled. The researcher is requesting a CVE ID for the issue.

oss-security·Sep 10, 01:12 UTC · 6d agoVulnerability1

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I accidentally turned LLM memory into program analysis

A pwning.systems write-up describes how LLM memory functionality was unexpectedly repurposed into a program analysis technique.

A security research post on pwning.systems describes the author's discovery that LLM memory behavior effectively functioned as program analysis. The write-up is hosted on a security-focused blog and surfaced via a security-tagged link aggregator. Detailed technical content is not included in this feed, limiting verifiable specifics.

Lobsters · security·Aug 29, 03:16 UTC · 18d agoResearch1

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The AI Kill Switch Act is repeating the Clipper Chip’s mistakes

Op-ed argues the AI Kill Switch Act repeats the Clipper Chip's mistake by mandating backdoors into frontier AI systems.

The op-ed criticizes the AI Kill Switch Act, sponsored by Reps. Ted Lieu and Nathaniel Moran, which would let CISA require frontier AI labs to build the ability to throttle, suspend, or shut down their systems. The author compares this to the 1993 Clipper Chip, whose Law Enforcement Access Field was found flawed in 1994, and argues mandated kill switches would create deliberate weaknesses in AI agents embedded in banking, power grids and other critical infrastructure. It also flags the bill's exemption of red-teaming incidents and CAISI's incomplete agent security standards, recommending mandatory red-teaming and liability frameworks instead.

CyberScoop·Aug 31, 10:00 UTC · 16d agoAI policy

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PHAT: PHotonic Accelerator for TFHE

PHAT photonic accelerator using optically addressed phase-change memory speeds TFHE bootstrapping FFTs 2.14x-5.10x over the prior ASIC accelerator.

Researchers propose PHAT, an electro-photonic accelerator for TFHE fully homomorphic encryption built on optically addressed phase-change memory (OPCM) processing-in-memory. The architecture adds OPCM-based FFT units, a twiddle-stationary dataflow, and a scheduling mechanism to maximize FFT utilization for TFHE bootstrapping. It achieves 2.14x-5.10x speedups across four real-world TFHE workloads versus the state-of-the-art ASIC accelerator, improving feasibility of privacy-preserving computation in the cloud.

arXiv cs.CR·Sep 10, 14:30 UTC · 6d agoResearch

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Forgetting Without Restarting: Execution-State Unlearning for Stateful LLM Agents

Researchers propose provenance-guided selective replay letting LLM agents forget revoked information without restarts, matching full reset behavior.

The paper formalizes execution-state unlearning for stateful LLM agents, requiring that agents behave as if a revoked memory record was never observed across transcripts, compressed memory, tool plans, and KV caches. It proves exact unlearning requires at least T-τ+1 recomputed transitions and that Provenance-Guided Selective Replay attains this bound via a provenance graph, KV cache cropping, and sanitized replay. In audits across three agent suites, nine baselines, and three model families, memory deletion left leakage unchanged, instruction-based forgetting collapsed under elicitation (Leak@probes = 1.00), and selective replay matched full resets at up to 9x fewer recomputed tokens.

arXiv cs.CR·Sep 4, 08:31 UTC · 12d agoAI safety & security1

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CertiFlash: A Formal Verification Framework for Flash Translation Layers in Computational Solid State Drives

CertiFlash provides machine-checked formal verification of SSD flash translation layers, proving isolation, integrity, and ownership invariants to prevent tenant data leaks.

CertiFlash is an open-source formal verification framework for Flash Translation Layers (FTL) in computational SSDs, mechanized in the Rocq proof assistant. It shows that a faulty FTL can corrupt device state at five surfaces (e.g., leaking data between tenants or dropping integrity tags), demonstrated on a DaisyPlus OpenSSD. Designers prove once that every operation of a general FTL model preserves a global invariant covering mapping, isolation, integrity, ownership, and allocation; new designs need only discharge five hypotheses. Across four case studies, added effort was 27-3,231 lines against a 16,489-line framework.

arXiv cs.CR·Sep 9, 15:44 UTC · 7d agoResearch1

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Towards Standardized Evaluation of GPU Memory Safety with GMSBench

GMSBench provides 149 CUDA tests covering spatial, temporal, and concurrency GPU memory errors, exposing detection gaps in Compute Sanitizer.

GMSBench is a GPU memory safety benchmark comprising 149 self-contained CUDA tests spanning spatial, temporal, and concurrency errors across different GPU memory spaces and execution scenarios. The authors evaluate NVIDIA's Compute Sanitizer across multiple GPU architectures using the suite, exposing gaps in its detection coverage. The benchmark offers a standardized foundation for comparative evaluation of GPU memory safety mechanisms.

arXiv cs.CR·Sep 8, 15:11 UTC · 8d agoResearch

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Testing race conditions with memory access tracing and stack-based delay injection

Google Project Zero released MAccConc, Linux kernel tooling that traces memory accesses to explore and test race condition interleavings.

A Google Project Zero researcher published MAccConc (Memory Access Concurrency), tooling for exploring possible interleavings of multithreaded test cases in the Linux kernel, available on GitHub. The tools use KCOV with ASAN outline-mode instrumentation to record per-access memory traces, enabling automatic testing of all A-B-A interleavings plus terminal and GUI explorers for manual analysis. The work targets confirming race condition candidates, building reliable regression tests, and enabling concurrency fuzzing, drawing on ideas from SKI and Ned Williamson's sockfuzzer.

Google Project Zero·Sep 8, 07:00 UTC · 8d agoResearch1

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Windows memory integrity switches on automatically for eligible devices in October 2026

Microsoft's Windows quality updates will automatically enable memory integrity and Virtualization-based Security on eligible devices starting October 2026.

Beginning in October 2026, Windows quality updates will automatically enable memory integrity on eligible devices and turn on Virtualization-based Security where it is not already running. Memory integrity restricts kernel-mode execution to trusted, signed code and drivers, blocking kernel compromise and rootkits. Microsoft said existing administrator decisions remain in effect, and readiness checks weigh hardware capability, compatibility, and performance. Memory integrity also underpins hotpatch updates that install without a reboot, so unprotected devices are excluded from that servicing model.

Help Net Security·Sep 3, 00:00 UTC · 13d agoAdvisory

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[AINews] Hot Chips: OpenAI’s Jalapeño, Cerebras CS-5, Groq 3 LPX, Apple M6

OpenAI unveiled Jalapeno custom inference chip claiming 1.5-1.9x better perf-per-watt than NVIDIA GB200/GB300, deploying in-house by year-end.

At the 37th Hot Chips conference, OpenAI published first benchmark details for its custom Jalapeno inference chip, claiming 1.5-1.9x more work per watt, 1.7-3.6x lower end-to-end latency, and 2.1-4.1x higher interactive-workload performance versus NVIDIA GB200/GB300, with the 700W-rated part staying at or below 550W in tests. Deployment into OpenAI's own infrastructure begins by year-end, with Gen 2 deep in development and Gen 3 underway. OpenAI also said GPT-Astra and Codex helped write low-level kernels, reportedly 1.5-1.8x faster than human-expert code for selected attention and MoE blocks. Cerebras CS-5, Groq 3 LPX and Apple M6 were also featured at the conference.

Latent Space·Aug 27, 01:31 UTC · 20d agoAI industry

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Give Your Coding Agents a Memory You Own

Hugging Face introduces Funes, a tool that gives coding agents persistent, self-owned memory outside vendor clouds.

A Hugging Face blog post presents Funes, an approach for giving coding agents a persistent memory that developers own and control. The piece targets agent workflows where context must survive across sessions without ceding data to third-party services. No article body was available in the feed, so specifics beyond the title are limited.

Hugging Face Blog·Sep 3, 00:00 UTC · 13d agoAI tools & infra1

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Chypothermia: Clock Freezing for Static Side-channel Attacks

Chypothermia attack uses cryogenic cooling to disable clock and voltage sensors, evading detection and blocking key zeroization on OpenTitan root of trust.

Chypothermia is a static side-channel attack that exposes chips to cryogenic temperatures, disrupting on-chip mixed-signal components to disable the clock sensor, clock generation circuit, and voltage sensors without electrical tampering. Combined with Chypnosis (IEEE S&P 2026), it halts the clock while evading temperature-based anomaly detection. It was implemented on multiple FPGA/SoC platforms and applied to the OpenTitan root of trust's alert handler, evading detection and preventing key zeroization. The authors also propose an FPGA-compatible self-heating sensor as a countermeasure.

arXiv cs.CR·Sep 10, 12:12 UTC · 6d agoResearch

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Continual Learning Mechanisms Compose for Long-Horizon Memorization

Composing data, function, and weight anchors with merged LoRA raises 100-task long-horizon retention from 1.2% to 34.9% in continual fine-tuning.

The paper introduces long-horizon memorization: a model learns 100 query-answer tasks through continual supervised fine-tuning without retaining earlier examples or receiving task identifiers at inference. No single continual learning mechanism maintains strong retention at this horizon, so the authors compose complementary mechanisms along data/function/weight anchors and low-rank allocation rules. The best method combining all three anchors with merged LoRA ranks among the top 3 methods on all three datasets and raises average final retention from 1.2% to 34.9%, a 28-fold improvement.

Hugging Face daily papers·Sep 6, 20:00 UTC · 10d agoAI research

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