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Power, Performance, and Area of HPC-Based Malware Detectors: An FPGA and Open-PDK ASIC Study

arXiv cs.CRby Alireza Abolhasani Zeraatkar ()1 min read1 · 1 read
Read at arxiv.org
AI summary · grok-4.7Summaries by Vani AI

FPGA and ASIC study finds tree-based HPC malware detectors use far less area and energy than function-based models.

The paper measures area, power, and timing of hardware malware detectors that classify programs from hardware performance counters. A pipeline rebuilds trained models into synthesizable RTL, checks them against a bit-accurate golden model, and evaluates FPGA and open-PDK ASIC implementations. Tree- and rule-based ensembles use nearly an order of magnitude less area and several times less energy than function-based classifiers. Cutting HPC inputs to a processor's concurrent-counter limit keeps detection performance while further reducing area, power, and delay.

Key facts
  • Ensemble HPC detectors lead prior detection metrics.
  • Tree and rule models need far less area and energy.
  • Fewer concurrent counters preserve detection while cutting delay.
  • Designs were validated against bit-accurate golden RTL models.
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Tags
malware-detectionhardware-performance-countersfpgaasicensembleopen-pdk

From the original article

1 min read at arxiv.org

Hardware malware detectors (HMDs) classify programs as benign or malicious based on hardware performance counter (HPC) data. Previous studies have shown that ensemble classifiers outperform other classifiers on detection metrics. However, the area, power, and timing costs of HMDs remain open questions.

arXiv cs.CR

By Alireza Abolhasani Zeraatkar · arxiv.org

Read the full article at arXiv cs.CR

A short excerpt; the article and its images belong to the publisher. Summary, key facts and assessment above are AI-written from the article and can be wrong.