Power, Performance, and Area of HPC-Based Malware Detectors: An FPGA and Open-PDK ASIC Study
FPGA and ASIC study finds tree-based HPC malware detectors use far less area and energy than function-based models.
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Stories tagged #asic
Efficient TCitH-Based Alternatives to SLH-DSA: Cross-Layer ASIC Design of Mirath
A 22nm Mirath ASIC signs 17.8x faster than same-node SLH-DSA while using 58% less area.
Locus: A Framework for Exploring and Optimizing Point Addition Hardware for Zero-Knowledge Proofs
Locus framework automates ASIC and FPGA point-addition designs for elliptic curves, achieving 2.71x speedups and 3.11x area reductions for ZKPs.