Terracotta: Enabling the Adoption of New DRAM Techniques via a Flexible DRAM Interface and Memory Controller
Terracotta programs a DDR5 memory controller so new DRAM techniques deploy without interface redesigns.
Terracotta proposes custom DRAM command extensions and a programmable memory controller so new DRAM techniques can be deployed on DDR5 without redesigning the interface and controller. Across processing-using-DRAM, low-cost maintenance, subarray-level parallelism, and latency reduction, it retained more than 96% of custom-implementation performance. Combining two techniques outperformed either technique alone. Reported overheads were 0.6–3.2% DRAM energy, 0.03% area, and 0.56% power, and the source code is public.
- Flexible DDR5 commands and a programmable controller avoid redesigns.
- Retains over 96% of custom-implementation performance on four techniques.
- Stacking two techniques beat either Terracotta technique alone.
- Overheads were low: up to 3.2% energy, 0.03% area, 0.56% power.
- Products
- DDR5Terracotta
- Organizations
- CMU SAFARI
From the original article
1 min read at arxiv.orgDRAM continues to limit the performance, energy efficiency, and robustness of modern systems. Many prior works propose DRAM techniques that support in-DRAM computation, improve memory access latency and parallelism, and enhance DRAM maintenance and reliability. However, adopting each new technique requires repeated modifications to the rigid DRAM interface and memory controller, hindering its deployment.
By Harsh Songara · arxiv.org
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