AutoTrans: AI-Assisted Automatic Translation of Security Assertions for RISC-V Processors
AutoTrans uses LLMs with regex extraction and formal verification to automatically translate security assertions across RISC-V processors, achieving 78% unattended acceptance.
AutoTrans is an automated framework for translating verified security assertions between RISC-V processor targets, where manual translation takes hours per assertion. It combines a regex-based SystemVerilog signal extractor to prevent LLM signal hallucination, a pinned prompt template yielding byte-identical prompts resilient to model updates, and JasperGold FPV formal verification of generated assertions. Applied with DeepSeek V4 to translate assertions between RISC-V targets such as IBEX and NS31A, it achieves a 78% automatic translation acceptance rate without human intervention and 100% after human refinement.
- Automates cross-target translation of verified security assertions, cutting hours-per-assertion manual work
- Regex-based SystemVerilog extractor prevents LLM signal hallucination in generated assertions
- Pinned prompt template produces byte-identical prompts, resilient to model updates
- JasperGold FPV verification yields 78% auto acceptance, 100% after human refinement
- Vendors
- Cadence
- Products
- JasperGold
- AI models
- DeepSeek V4
From the original article
1 min read at arxiv.orgReusing a set of verified security assertions across RISC-V processor targets remains one of the most expensive bottlenecks in hardware security verification. Manual translation takes hours per assertion.
By Sharjeel Imtiaz · arxiv.org
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