EquivSVA: A Formally Verified Dataset of Behavioral Assertions Across Equivalent RTL Implementations
EquivSVA provides 120 verified RTL behavior families to test whether LLM assertions capture observable behavior.
Stories per day · 30 days
2 stories, newest first · one card per story
Stories tagged #systemverilog
AutoTrans: AI-Assisted Automatic Translation of Security Assertions for RISC-V Processors
AutoTrans uses LLMs with regex extraction and formal verification to automatically translate security assertions across RISC-V processors, achieving 78% unattended acceptance.