SLED-IFV: Solver-Validated LLM-Guided Decomposition for Scalable Hardware Information-Flow Verification
SLED-IFV uses solver-checked LLM decompositions to speed hardware information-flow proofs by up to 603x.
Researchers present SLED-IFV, a closed-loop flow in which an LLM proposes semantic decompositions for self-composed hardware information-flow proofs while a formal backend remains the sole acceptance authority. Functional simplification replaces proof-hard RTL with a validated over-approximate summary, and relational strengthening exposes cross-copy public-control facts needed for induction. On nine benchmarks built from real RTL, it reached up to 603x solver-only speedup and completed two proofs that had timed out after 12 hours.
- LLM proposes decompositions; only the formal verifier accepts proofs.
- Functional simplification replaces hard RTL regions with validated summaries.
- Relational strengthening exposes cross-copy facts needed for induction.
- Up to 603x speedup; two 12-hour timeouts became completed proofs.
From the original article
1 min read at arxiv.orgFormal hardware information-flow verification (IFV) provides strong guarantees against secret-dependent timing and control behavior, but often scales poorly on realistic RTL.
By Liangtao Dai · arxiv.org
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