GI-RTL-Fuzz finds inconsistencies in major Verilog simulators
Grammar-guided LLM generation and differential testing exposed previously unknown linting and simulation mismatches.
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Stories tagged #rtl
RTL repair scores can miss whether models used the broken design
A new 459-case benchmark finds simulation and formal scoring can disagree, and specification-only baselines swing widely.
Back to the Future: Rethinking EDA Infrastructure for Agentic Systems in Chip Design Verification
BTTF uses multi-agent SQL over simulation dumps to automate chip-design verification queries.
SoK: You Find What You Seek: Rethinking Oracles, Guidance, and Input Generation in Hardware Fuzzing
A survey of 52 hardware fuzzers says campaigns only find bugs they can reach, recognize, and prioritize.
EquivSVA: A Formally Verified Dataset of Behavioral Assertions Across Equivalent RTL Implementations
EquivSVA provides 120 verified RTL behavior families to test whether LLM assertions capture observable behavior.
SLED-IFV: Solver-Validated LLM-Guided Decomposition for Scalable Hardware Information-Flow Verification
SLED-IFV uses solver-checked LLM decompositions to speed hardware information-flow proofs by up to 603x.
Trust, but Validate the Instrument: Auditing AI-Generated RTL Verification Plans on Authored Security-Regression Proxies
Researchers release SecTB-RTL, an auditable framework showing that AI-generated RTL verification plans passing provider schema checks can still fail execution validity.