HPS-PEC uses register renaming for privacy-enhanced CPU computing
Across 25 VIP-Bench benchmarks, encrypted code ran 3.41x native time and 1.26x faster than a sequestered unit.
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27 stories, newest first · one card per story
Stories tagged #hardware-security
EVAX paper proposes on-demand defenses for microarchitectural attacks
Authors report cutting InvisiSpec overhead from 27% to 1.26% and Fencing from 74% to 3.45%.
SensorGuard-RV protects sensor data on RISC-V devices
SensorGuard-RV delivers protected samples to registers in 51.9 μs using hardware encryption.
arXiv demonstrates secure debug re-enablement on RP2350
Photon-emission microscopy and laser fault injection allow re-enabling secure debug on RP2350, restoring sustained access after reset.
Software PUFs surveyed for hardware roots of trust in edge AI
Survey of 37 software PUF works highlights trade-offs for boot-time key derivation and response latency in edge AI.
Stacked hardware controller enhances Edge AI security
A stacked hardware security controller enables low-overhead anomaly detection in Edge AI systems using performance counters.
Keystream capping improves dynamic logic locking against SAT and structural attacks
Internal key-gate placement with keystream reuse capping raises attack search space to over 10^45 and prevents key extraction.
Florida researchers fold hardware-security labs into core engineering courses
Nine modules tie security exercises to existing design topics; three were assessed with 25 survey respondents.
Automotive Hardware Attacks: An Architect's Guide to TARA
ISO/SAE 21434 TARA underrates physical hardware attacks; authors add a hardware-aware feasibility method.
A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience
First dToF LiDAR SoC with dual-domain fingerprinting rejects spoofed laser echoes, protecting 73% of the point cloud versus 0% unprotected.
The Achilles' Heel of Partial Reconfiguration: Optical Side-Channel Leakage on the 7-Series ICAP
Researchers recover plaintext FPGA configuration from AMD 7-Series ICAP using optical probing during partial reconfiguration.
NVIDIA wants AI agent safety enforced in silicon, not left to the agent
NVIDIA released an open platform that confines AI agents with runtime policies and separate-hardware monitoring.
Application Agnostic EM Side-Channel Emanations of the FPGA Clock Distribution Network
FPGA electromagnetic leakage rose about 1.3 times when clock-resource use increased from 25% to 90%.
SLED-IFV: Solver-Validated LLM-Guided Decomposition for Scalable Hardware Information-Flow Verification
SLED-IFV uses solver-checked LLM decompositions to speed hardware information-flow proofs by up to 603x.
TigerByte Cyber Emerges From Stealth With $3 Million in Funding
TigerByte Cyber emerged from stealth with $3M in seed funding to deliver hardware-enforced cybersecurity for AI and edge devices.
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SFPF: Spatio-Frequency Polarization Fingerprint for Anomalous Wireless Device Detection
SFPF fingerprinting detects swapped wireless hardware better than RF or single-direction polarization fingerprints.
Trust, but Validate the Instrument: Auditing AI-Generated RTL Verification Plans on Authored Security-Regression Proxies
Researchers release SecTB-RTL, an auditable framework showing that AI-generated RTL verification plans passing provider schema checks can still fail execution validity.
Analog Pin Directionality as an Exfiltration Attack Surface in Mixed-Signal ICs
Researchers demonstrate exfiltration through nominally input-only analog pins in mixed-signal ICs, recovering data at 10 kbps on a 55nm PPG front-end.
s-MDM: Generative Virtualization of Multi-Device Hardware Variations for Portable DL-SCA
Researchers present s-MDM, a generative framework synthesizing virtual device profiles to improve cross-device portability of deep learning side-channel analysis.
New hardware device can RAM into encrypted memory, expose your data
Researchers built a $200 DDR5 interposer that silently drops memory writes to break TDX, SGX, and SEV-SNP confidential VM integrity, requiring physical access.
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CHERI-D Reincarnate: efficient multicore CHERI temporal memory safety through allocation reincarnation (draft version)
CHERI-D Reincarnate adds allocation reincarnation to CHERI, quarantining generation IDs instead of memory to cut temporal memory-safety overheads on multicore systems.
Chypothermia: Clock Freezing for Static Side-channel Attacks
Chypothermia attack uses cryogenic cooling to disable clock and voltage sensors, evading detection and blocking key zeroization on OpenTitan root of trust.
Signing TLS handshakes inside a TPM
Blog post demonstrates signing TLS handshakes in Go with a TPM-held private key; full text was unavailable behind an Anubis challenge.
Has anybody seen my keys? A key-hierarchy strategy for rack-level security
Oxide's RFD 0301 proposes a rack-level key hierarchy using Shamir secret sharing and a trust quorum to protect data-at-rest keys.
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