arXiv evaluates randomized caches for side-channel protection
Original title: Randomized Caches in Hardware: Challenges and Trade-offs
FPGA implementation of four randomized cache designs in a multi-core RISC-V SoC shows pipelining alone insufficient and redesign needed to limit frequency loss to 10% below baseline.
Researchers implemented CEASER-S ScatterCache SassCache and MIRAGE as the last-level cache in a multi-core out-of-order RISC-V system-on-chip. They identified common and design-specific hardware challenges and developed practical solutions. Complete FPGA evaluations on SPEC CPU 2017 and GAPBS workloads revealed that increased LLC access latency dominates IPC degradation. Hardware overhead varies by design with FPGA LUT usage rising 10-35% and ASIC area 1-14%.
- Four prominent randomized cache designs implemented
- Pipelining IDF alone insufficient in three variants
- Redesigning critical paths limits frequency loss to 10%
- Increased access latency reduces IPC by up to 5% for SPEC and 11% for GAPBS
- First full-system comparative evaluation on common platform
From the original article
1 min read at arxiv.orgRandomized caches protect against side-channel attacks by obfuscating the mapping of memory addresses to cache locations. Existing proposals typically describe architectural behavior, leaving practical hardware implementation challenges largely unexplored.
By Xinrui Wang · arxiv.org
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