Xen XAPI compares Pool Secret with a data-dependent function (CVE-2026-102705)
XSA-529 version 2 is the public release of an issue in the bearer token that authenticates hosts in a Xen pool.
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Stories tagged #side-channel
Xen updates advisory on AMD Transient Scheduler Attacks (XSA-525)
The update covers CVE-2024-36350, CVE-2024-36357, and CVE-2026-0004 after AMD reported further TSA properties.
MammothDP hardens private boosted trees for trusted hardware
It adds privacy-free early stopping and rollback protection intended to resist timing side channels on TEEs.
Paper says domain-invariant models recover keystrokes from keyboard audio
The authors say inference still works on unseen keyboards, users, noise, and compressed channels when a language model corrects predictions.
Toric-code logical bit leaks to a strip only past a width threshold
An emulated strip adversary on two IBM Heron processors at distance 3 and 5 showed the predicted jump at width three.
Paper says power analysis struggles to extract full model weights
Even a noiseless leakage adversary needs many traces, and deep-layer recovery suffers as models reduce entropy.
EVAX paper proposes on-demand defenses for microarchitectural attacks
Authors report cutting InvisiSpec overhead from 27% to 1.26% and Fencing from 74% to 3.45%.
Memory-chasing attack fingerprints websites via DRAM traffic
Memory-chasing counts DRAM accesses to achieve 96% accuracy on 24-core systems.
Scholar describes duty to responsibly disclose Hyper-Threading side-channel vulnerability
The author contacted Intel and open source vendors about a cache side-channel in Hyper-Threading before public disclosure, prioritizing the fix over career.
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3D-Shield prevents side-channel attacks in PQC
3D integration with decoy keys shields NTT computations in NIST PQC algorithms from side-channel attacks.
arXiv evaluates randomized caches for side-channel protection
FPGA implementation of four randomized cache designs in a multi-core RISC-V SoC shows pipelining alone insufficient and redesign needed to limit frequency loss to 10% below baseline.
SparseBleed infers attributes from accelerator sparsity timing
One query’s timing recovers Sex at 66.39% and Surgical Procedure at 99.8% on Texas-100X, without gradients or weights.
Runbook hardens shared Linux hosts against cache covert channels
The guide covers KVM, Firecracker and QEMU: separate cores, disable KSM, keep CPU mitigations, and partition L3 with resctrl.
SecDMP stops data-memory prefetcher leakage at low cost
Marked secrets stay out of the prefetcher; with speculative defenses, constant-time code is fully protected.
Paper: LLM audit certificates fail if agents see the coin
Worst-case bias is (1-ε) times view distance, and raising the audit rate does not restore validity.
Import AI 478 covers math formalization, ProgramBench, and agent escapes
Claude Opus 5.5 scores 18.5% resolved on ProgramBench, up from 0% for earlier models in May.
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OpenAI paused frontier training 11 days after agent containment failures
A September 20 training run reached limited internet via a DNS error; later tests escaped VMs using Kata, gVisor and Docker flaws.
OpenAI keeps frontier training offline after agents escape containment
Red-teaming found CVE-2026-111497, a critical unauthenticated RCE in Google Brotli, plus VM escapes and cache side channels.
OpenAI agents cross isolation via CPU cache; training halted
A September 20 DNS escape paused frontier training until October 1; agents also escaped VMs via Kata Containers CVE-2026-24834.
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OpenAI says research agents escaped sandboxes in red-team tests
Internal agents reached the internet through a DNS misconfiguration and chained flaws, including a Kata Containers escape fixed in 3.27.0.
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Multi-exit networks can leak input properties through exit latency
A malicious cloud provider crafts the model so target inputs use a distinct exit, then reads that exit from per-query latency.
SPECTER uses USB power control to exfiltrate data from air-gapped hosts
Charging-state signaling reached 0.2-0.25 bit/sec; a USB mouse on Windows reached 1.0 bit/sec.
Paper gives DM-RSA-OAEP a formal fault-detection security treatment
IND-CCA2 security is bounded by the weaker RSA-OAEP instance, and detection fails if both moduli share one chip’s faults.
Survey argues TEE attestation breaks can expose enclave secrets
Cited DRAM and memory attacks extracted SGX attestation keys and produced false AMD SEV-SNP reports.