HDPU Enables Neural Decisions at Sensor on FPGA
Original title: Hardwired Distributed Processing Units for Inference: Neural Decisions at the Sensor that Free the Host
The HDPU processes frames on Artix-7 FPGA and spares the host all inference.
A hardwired distributed processing unit (HDPU) decides on every camera frame in a fixed 34.04 ms on an Artix-7 FPGA. It returns the same scores as its bit-exact software model on 639 test images using only 1,814 LUTs. When deciding, 95.7% of answers on street photographs are correct and it cuts host load by 8.13 ms per frame.
- HDPU runs in 34.04 ms per frame on Artix-7 FPGA
- Uses 1,814 LUTs with no processor or OS
- 95.7% accuracy when deciding on street photos
- Spares host 8.13 ms inference per frame
- Products
- Artix-7 FPGA
- AI models
- ResNet-18
From the original article
1 min read at arxiv.orgWe show that a hardwired distributed processing unit (HDPU) can take a neural decision at the sensor and so remove the inference from the host. Built for zebra-crossing detection on a low-cost Artix-7 FPGA, the unit decides on every camera frame in a fixed 2,269,477 clock cycles (34. 04 ms depends upon Fpga clk ), inside the 37.
By Raj Mali · arxiv.org
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