HDPU Enables Neural Decisions at Sensor on FPGA
The HDPU processes frames on Artix-7 FPGA and spares the host all inference.
Stories per day · 30 days
4 stories, newest first · one card per story
Stories tagged #hardware-acceleration
Locus: A Framework for Exploring and Optimizing Point Addition Hardware for Zero-Knowledge Proofs
Locus framework automates ASIC and FPGA point-addition designs for elliptic curves, achieving 2.71x speedups and 3.11x area reductions for ZKPs.
OptiPrime: Optimizing Private Inference through Protocol-Hardware Co-design
OptiPrime co-designs HE-MPC protocols with hardware acceleration to remove network communication bottlenecks in private DNN inference, beating Cheetah by up to 5.7x.
PHAT: PHotonic Accelerator for TFHE
PHAT photonic accelerator using optically addressed phase-change memory speeds TFHE bootstrapping FFTs 2.14x-5.10x over the prior ASIC accelerator.