RV2GC rebuilds garbling around fixed RISC-V instruction circuits
Original title: RV2GC: Reconstructing the Garbling Boundary in a RISC-V Garbled Processor
On nine benchmarks, ARM2GC-to-RV2GC runtime ratios ranged from 12.81 to 4,043, with public scheduling kept outside the circuits.
RV2GC reconstructs the garbling boundary around a fixed library of RISC-V instruction circuits so a garbled processor can reuse circuits without re-evaluating processor-wide structures. Public scheduling and operand routing stay outside the circuit, while label-encoded state links independently invoked instructions. A Conditional-execution Stack and protected commits handle secret-dependent branches, bounded loops, and secret-indexed memory under public scheduling. The largest listed instruction circuit has 3,386 gates.
Unconfirmed: Reported speedups and circuit sizes are the authors' measurements, not an independent evaluation.
- Runtime ratios versus ARM2GC span 12.81 to 4,043 across nine benchmarks.
- The largest instruction circuit is 3,386 gates.
- That circuit is 2.044% of the 256-byte Amber processor and 0.393% of the 4,096-byte one.
- Comparisons also cover schedule storage, communication, and secret-dependent execution cost.
From the original article
1 min read at arxiv.orgProgrammable garbled-circuit execution must balance the benefits of cross-program reuse against the cost of repeated work during secure execution. A complete garbled processor provides a fixed circuit for many programs, but its evaluator repeatedly visits processor-wide structures even when only a small part performs the current protected computation.
By Zixiao Feng · arxiv.org
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