Efficient HQC Implementations on RISC-V: A Cross-Layer Design Space Exploration
A 29,920-configuration RISC-V study finds faster, smaller HQC implementations on FPGA.
The authors present a broad RISC-V hardware/software design-space study of HQC, a post-quantum key-encapsulation mechanism selected for standardization. A parametrizable framework characterizes 29,920 configurations across all three HQC security levels on FPGA. Pareto-optimal designs beat prior RISC-V HQC work, from 4.8x lower LUT use at 17% lower latency to 69.6x lower latency at 30% lower LUT use, and use up to 10.6x fewer block RAMs.
- Study explores 29,920 RISC-V architectural configurations for HQC on FPGA.
- Configurations cover all three HQC security levels.
- Pareto designs cut LUT use up to 4.8x or latency up to 69.6x versus prior work.
- Best designs also use up to 10.6x fewer block RAMs.
From the original article
1 min read at arxiv.orgRISC-V-based hardware/software co-design has become an established methodology for implementing post-quantum cryptography (PQC) on embedded devices. Its software programmability, extensible instruction-set architecture, and optional dedicated accelerators create a broad design space that offers the flexibility required for crypto-agility and post-deployment updates.
By Maximilian Schöffel · arxiv.org
A short excerpt; the article and its images belong to the publisher. Summary, key facts and assessment above are AI-written from the article and can be wrong.